379 lines
11 KiB
C
379 lines
11 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/icu_lld.h
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* @brief STM32 ICU subsystem low level driver header.
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*
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* @addtogroup ICU
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* @{
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*/
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#ifndef _ICU_LLD_H_
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#define _ICU_LLD_H_
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#if HAL_USE_ICU || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief ICUD1 driver enable switch.
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* @details If set to @p TRUE the support for ICUD1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ICU_USE_TIM1) || defined(__DOXYGEN__)
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#define STM32_ICU_USE_TIM1 FALSE
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#endif
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/**
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* @brief ICUD2 driver enable switch.
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* @details If set to @p TRUE the support for ICUD2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ICU_USE_TIM2) || defined(__DOXYGEN__)
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#define STM32_ICU_USE_TIM2 FALSE
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#endif
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/**
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* @brief ICUD3 driver enable switch.
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* @details If set to @p TRUE the support for ICUD3 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ICU_USE_TIM3) || defined(__DOXYGEN__)
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#define STM32_ICU_USE_TIM3 FALSE
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#endif
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/**
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* @brief ICUD4 driver enable switch.
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* @details If set to @p TRUE the support for ICUD4 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ICU_USE_TIM4) || defined(__DOXYGEN__)
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#define STM32_ICU_USE_TIM4 FALSE
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#endif
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/**
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* @brief ICUD5 driver enable switch.
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* @details If set to @p TRUE the support for ICUD5 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ICU_USE_TIM5) || defined(__DOXYGEN__)
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#define STM32_ICU_USE_TIM5 FALSE
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#endif
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/**
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* @brief ICUD8 driver enable switch.
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* @details If set to @p TRUE the support for ICUD8 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_ICU_USE_TIM8) || defined(__DOXYGEN__)
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#define STM32_ICU_USE_TIM8 FALSE
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#endif
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/**
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* @brief ICUD1 interrupt priority level setting.
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*/
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#if !defined(STM32_ICU_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ICU_TIM1_IRQ_PRIORITY 7
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#endif
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/**
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* @brief ICUD2 interrupt priority level setting.
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*/
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#if !defined(STM32_ICU_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ICU_TIM2_IRQ_PRIORITY 7
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#endif
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/**
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* @brief ICUD3 interrupt priority level setting.
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*/
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#if !defined(STM32_ICU_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ICU_TIM3_IRQ_PRIORITY 7
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#endif
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/**
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* @brief ICUD4 interrupt priority level setting.
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*/
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#if !defined(STM32_ICU_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ICU_TIM4_IRQ_PRIORITY 7
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#endif
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/**
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* @brief ICUD5 interrupt priority level setting.
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*/
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#if !defined(STM32_ICU_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ICU_TIM5_IRQ_PRIORITY 7
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#endif
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/**
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* @brief ICUD8 interrupt priority level setting.
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*/
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#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ICU_TIM8_IRQ_PRIORITY 7
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_ICU_USE_TIM1 && !STM32_HAS_TIM1
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#error "TIM1 not present in the selected device"
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#endif
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#if STM32_ICU_USE_TIM2 && !STM32_HAS_TIM2
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#error "TIM2 not present in the selected device"
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#endif
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#if STM32_ICU_USE_TIM3 && !STM32_HAS_TIM3
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#error "TIM3 not present in the selected device"
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#endif
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#if STM32_ICU_USE_TIM4 && !STM32_HAS_TIM4
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#error "TIM4 not present in the selected device"
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#endif
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#if STM32_ICU_USE_TIM5 && !STM32_HAS_TIM5
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#error "TIM5 not present in the selected device"
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#endif
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#if STM32_ICU_USE_TIM8 && !STM32_HAS_TIM8
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#error "TIM8 not present in the selected device"
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#endif
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#if !STM32_ICU_USE_TIM1 && !STM32_ICU_USE_TIM2 && \
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!STM32_ICU_USE_TIM3 && !STM32_ICU_USE_TIM4 && \
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!STM32_ICU_USE_TIM5 && !STM32_ICU_USE_TIM8
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#error "ICU driver activated but no TIM peripheral assigned"
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#endif
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#if STM32_ICU_USE_TIM1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM1"
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#endif
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#if STM32_ICU_USE_TIM2 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM2"
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#endif
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#if STM32_ICU_USE_TIM3 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM3"
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#endif
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#if STM32_ICU_USE_TIM4 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM4"
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#endif
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#if STM32_ICU_USE_TIM5 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM5"
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#endif
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#if STM32_ICU_USE_TIM8 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to TIM8"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ICU driver mode.
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*/
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typedef enum {
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ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
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ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
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} icumode_t;
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/**
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* @brief ICU frequency type.
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*/
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typedef uint32_t icufreq_t;
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/**
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* @brief ICU channel.
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*/
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typedef enum {
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ICU_CHANNEL_1 = 0, /**< Use TIMxCH1. */
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ICU_CHANNEL_2 = 1, /**< Use TIMxCH2. */
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} icuchannel_t;
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/**
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* @brief ICU counter type.
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*/
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typedef uint16_t icucnt_t;
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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/**
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* @brief Driver mode.
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*/
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icumode_t mode;
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/**
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* @brief Timer clock in Hz.
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* @note The low level can use assertions in order to catch invalid
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* frequency specifications.
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*/
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icufreq_t frequency;
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/**
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* @brief Callback for pulse width measurement.
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*/
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icucallback_t width_cb;
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/**
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* @brief Callback for cycle period measurement.
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*/
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icucallback_t period_cb;
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/**
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* @brief Callback for timer overflow.
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*/
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icucallback_t overflow_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief Timer input channel to be used.
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* @note Only inputs TIMx 1 and 2 are supported.
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*/
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icuchannel_t channel;
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} ICUConfig;
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/**
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* @brief Structure representing an ICU driver.
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*/
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struct ICUDriver {
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/**
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* @brief Driver state.
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*/
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icustate_t state;
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/**
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* @brief Current configuration data.
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*/
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const ICUConfig *config;
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#if defined(ICU_DRIVER_EXT_FIELDS)
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ICU_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Timer base clock.
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*/
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uint32_t clock;
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/**
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* @brief Pointer to the TIMx registers block.
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*/
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stm32_tim_t *tim;
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/**
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* @bried CCR register used for width capture.
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*/
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volatile uint32_t *wccrp;
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/**
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* @bried CCR register used for period capture.
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*/
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volatile uint32_t *pccrp;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Returns the width of the latest pulse.
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* @details The pulse width is defined as number of ticks between the start
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* edge and the stop edge.
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*
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* @param[in] icup pointer to the @p ICUDriver object
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* @return The number of ticks.
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*
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* @notapi
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*/
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#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
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/**
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* @brief Returns the width of the latest cycle.
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* @details The cycle width is defined as number of ticks between a start
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* edge and the next start edge.
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*
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* @param[in] icup pointer to the @p ICUDriver object
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* @return The number of ticks.
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*
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* @notapi
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*/
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#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_ICU_USE_TIM1 && !defined(__DOXYGEN__)
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extern ICUDriver ICUD1;
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#endif
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#if STM32_ICU_USE_TIM2 && !defined(__DOXYGEN__)
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extern ICUDriver ICUD2;
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#endif
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#if STM32_ICU_USE_TIM3 && !defined(__DOXYGEN__)
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extern ICUDriver ICUD3;
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#endif
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#if STM32_ICU_USE_TIM4 && !defined(__DOXYGEN__)
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extern ICUDriver ICUD4;
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#endif
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#if STM32_ICU_USE_TIM5 && !defined(__DOXYGEN__)
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extern ICUDriver ICUD5;
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#endif
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#if STM32_ICU_USE_TIM8 && !defined(__DOXYGEN__)
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extern ICUDriver ICUD8;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void icu_lld_init(void);
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void icu_lld_start(ICUDriver *icup);
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void icu_lld_stop(ICUDriver *icup);
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void icu_lld_enable(ICUDriver *icup);
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void icu_lld_disable(ICUDriver *icup);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_ICU */
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#endif /* _ICU_LLD_H_ */
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/** @} */
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