530 lines
17 KiB
C
530 lines
17 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC5xx/ADC_v1/adc_lld.h
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* @brief ADC Driver subsystem low level driver header.
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*
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* @addtogroup ADC
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* @{
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*/
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#ifndef _ADC_LLD_H_
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#define _ADC_LLD_H_
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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#include "spc5_adc.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Analog channel identifiers
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* @{
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*/
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#if SPC5_HAS_ADC0 || SPC5_HAS_ADC1 || defined(__DOXYGEN__)
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#define ADC_CHN_AN0 0U
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#define ADC_CHN_AN1 1U
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#define ADC_CHN_AN2 2U
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#define ADC_CHN_AN3 3U
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#define ADC_CHN_AN4 4U
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#define ADC_CHN_AN5 5U
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#define ADC_CHN_AN6 6U
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#define ADC_CHN_AN7 7U
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#define ADC_CHN_AN8 8U
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#define ADC_CHN_AN9 9U
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#define ADC_CHN_AN10 10U
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#define ADC_CHN_AN11 11U
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#define ADC_CHN_AN12 12U
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#define ADC_CHN_AN13 13U
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#define ADC_CHN_AN14 14U
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#define ADC_CHN_AN15 15U
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#endif
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/** @} */
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/**
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* @name ADC MCR register definitions
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* @{
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*/
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#define ADC_MCR_OWREN (1U << 31)
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#define ADC_MCR_WLSIDE (1U << 30)
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#define ADC_MCR_MODE (1U << 29)
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#define ADC_MCR_NSTART (1U << 24)
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#define ADC_MCR_JTRGEN (1U << 22)
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#define ADC_MCR_JEDGE (1U << 21)
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#define ADC_MCR_JSTART (1U << 20)
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#define ADC_MCR_CTUEN (1U << 17)
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#define ADC_MCR_ADCLKSEL (1U << 8)
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#define ADC_MCR_ABORTCHAIN (1U << 7)
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#define ADC_MCR_ABORT (1U << 6)
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#define ADC_MCR_ACKO (1U << 5)
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#define ADC_MCR_PWDN (1U << 0)
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/** @} */
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/**
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* @name ADC MSR register definitions
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* @{
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*/
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#define ADC_MSR_NSTART (1U << 24)
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#define ADC_MSR_JABORT (1U << 23)
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#define ADC_MSR_JSTART (1U << 20)
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#define ADC_MSR_CTUSTART (1U << 16)
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#define ADC_MSR_CHADDR (1U << 9)
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#define ADC_MSR_ACKO (1U << 5)
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#define ADC_MSR_ADCSTATUS (1U << 0)
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/** @} */
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/**
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* @name ADC ISR register definitions
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* @{
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*/
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#define ADC_ISR_EOCTU (1U << 4)
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#define ADC_ISR_JEOC (1U << 3)
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#define ADC_ISR_JECH (1U << 2)
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#define ADC_ISR_EOC (1U << 1)
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#define ADC_ISR_ECH (1U << 0)
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/** @} */
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/**
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* @name ADC IMR register definitions
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* @{
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*/
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#define ADC_IMR_MSKEOCTU (1U << 4)
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#define ADC_IMR_MSKJEOC (1U << 3)
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#define ADC_IMR_MSKJECH (1U << 2)
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#define ADC_IMR_MSKEOC (1U << 1)
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#define ADC_IMR_MSKECH (1U << 0)
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/** @} */
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/**
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* @name ADC DMAE register definitions
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* @{
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*/
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#define ADC_DMAE_DCLR (1U << 1)
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#define ADC_DMAE_DMAEN (1U << 0)
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/** @} */
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/**
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* @name ADC CDR register definitions
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* @{
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*/
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#define ADC_CDR_VALID (1U << 19)
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#define ADC_CDR_OVERW (1U << 18)
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#define ADC_CDR_RESULT (1U << 16)
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#define ADC_CDR_CDATA_LEFT (1U << 6)
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#define ADC_CDR_CDATA_RIGHT (1U << 0)
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/** @} */
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/**
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* @name ADC Wathdog ISR definitions
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* @{
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*/
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#define ADC_ISR_AWD3_HT (1U << 7)
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#define ADC_ISR_AWD2_HT (1U << 6)
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#define ADC_ISR_AWD1_HT (1U << 5)
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#define ADC_ISR_AWD0_HT (1U << 4)
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#define ADC_ISR_AWD3_LT (1U << 3)
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#define ADC_ISR_AWD2_LT (1U << 2)
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#define ADC_ISR_AWD1_LT (1U << 1)
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#define ADC_ISR_AWD0_LT (1U << 0)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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#if SPC5_HAS_ADC0 || defined(__DOXYGEN__)
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/**
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* @brief ADCD1 driver enable switch.
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* @details If set to @p TRUE the support for ADC0 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC0) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC0 FALSE
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#endif
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/**
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* @brief ADC0 EOC interrupt priority level setting.
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*/
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#if !defined(SPC5_ADC_ADC0_EOC_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC0_EOC_PRIORITY 12
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#endif
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/**
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* @brief ADC0 ER interrupt priority level setting.
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*/
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#if !defined(SPC5_ADC_ADC0_ER_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC0_ER_PRIORITY 12
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#endif
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/**
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* @brief ADC0 WD interrupt priority level setting.
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*/
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#if !defined(SPC5_ADC_ADC0_WD_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC0_WD_PRIORITY 12
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#endif
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/**
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* @brief ADC0 DMA IRQ priority.
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*/
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#if !defined(SPC5_ADC_ADC0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC0_DMA_IRQ_PRIO 12
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#endif
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/**
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* @brief ADC0 peripheral configuration when started.
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* @note The default configuration is 1 (always run) in run mode and
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* 2 (only halt) in low power mode. The defaults of the run modes
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* are defined in @p hal_lld.h.
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*/
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#if !defined(SPC5_ADC_ADC0_START_PCTL) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#endif
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/**
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* @brief ADC0 peripheral configuration when stopped.
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* @note The default configuration is 0 (never run) in run mode and
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* 0 (never run) in low power mode. The defaults of the run modes
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* are defined in @p hal_lld.h.
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*/
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#if !defined(SPC5_ADC_ADC0_STOP_PCTL) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#endif
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#endif
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#if SPC5_HAS_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief ADCD2 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_ADC_USE_ADC1) || defined(__DOXYGEN__)
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#define SPC5_ADC_USE_ADC1 FALSE
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#endif
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/**
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* @brief ADC1 EOC interrupt priority level setting.
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*/
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#if !defined(SPC5_ADC_ADC1_EOC_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC1_EOC_PRIORITY 12
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#endif
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/**
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* @brief ADC1 ER interrupt priority level setting.
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*/
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#if !defined(SPC5_ADC_ADC1_ER_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC1_ER_PRIORITY 12
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#endif
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/**
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* @brief ADC1 WD interrupt priority level setting.
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*/
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#if !defined(SPC5_ADC_ADC1_WD_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC1_WD_PRIORITY 12
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#endif
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/**
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* @brief ADC1 DMA IRQ priority.
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*/
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#if !defined(SPC5_ADC_ADC1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC1_DMA_IRQ_PRIO 12
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#endif
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/**
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* @brief ADC1 peripheral configuration when started.
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* @note The default configuration is 1 (always run) in run mode and
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* 2 (only halt) in low power mode. The defaults of the run modes
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* are defined in @p hal_lld.h.
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*/
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#if !defined(SPC5_ADC_ADC1_START_PCTL) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#endif
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/**
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* @brief ADC1 peripheral configuration when stopped.
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* @note The default configuration is 0 (never run) in run mode and
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* 0 (never run) in low power mode. The defaults of the run modes
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* are defined in @p hal_lld.h.
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*/
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#if !defined(SPC5_ADC_ADC1_STOP_PCTL) || defined(__DOXYGEN__)
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#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#endif
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !SPC5_HAS_ADC0
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#error "ADC0 not present in the selected device"
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#endif
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#if !SPC5_HAS_ADC1
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#error "ADC1 not present in the selected device"
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#endif
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#if !SPC5_ADC_USE_ADC0 && !SPC5_ADC_USE_ADC1
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADC clock frequency.
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*/
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typedef enum {
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HALF_PERIPHERAL_SET_CLOCK_FREQUENCY = 0, /**< ADC clock frequency is half Peripheral Set Clock frequency. */
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PERIPHERAL_SET_CLOCK_FREQUENCY = 1 /**< ADC clock frequency is equal to Peripheral Set Clock frequency. */
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} adc_clock;
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/**
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* @brief ADC thresholds.
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*/
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typedef enum {
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ADC_THRHLR_DISABLED = 0, /**< Watchdog threshold disabled. */
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ADC_THRHLR_HIGHER = 1, /**< Watchdog higher threshold enabled. */
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ADC_THRHLR_LOWER = 2, /**< Watchdog lower threshold enabled. */
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ADC_THRHLR_BOTH_HL = 3, /**< Watchdog higher and lower thresholds enabled.*/
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} adcthrhlr_t;
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/**
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* @brief ADC sample data type.
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*/
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typedef uint16_t adcsample_t;
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/**
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* @brief Channels number in a conversion group.
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*/
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typedef uint16_t adc_channels_num_t;
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/**
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* @brief Possible ADC failure causes.
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* @note Error codes are architecture dependent and should not relied
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* upon.
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*/
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typedef enum {
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ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
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ADC_ERR_AWD0_HT = 1, /**< Watchdog 0 triggered Higher Threshold. */
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ADC_ERR_AWD0_LT = 2, /**< Watchdog 0 triggered Lower Threshold. */
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ADC_ERR_AWD1_HT = 3, /**< Watchdog 1 triggered Higher Threshold. */
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ADC_ERR_AWD1_LT = 4, /**< Watchdog 1 triggered Lower Threshold. */
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ADC_ERR_AWD2_HT = 5, /**< Watchdog 2 triggered Higher Threshold. */
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ADC_ERR_AWD2_LT = 6, /**< Watchdog 2 triggered Lower Threshold. */
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ADC_ERR_AWD3_HT = 7, /**< Watchdog 3 triggered Higher Threshold. */
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ADC_ERR_AWD3_LT = 8, /**< Watchdog 3 triggered Lower Threshold. */
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} adcerror_t;
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/**
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* @brief Type of a structure representing an ADC driver.
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*/
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typedef struct ADCDriver ADCDriver;
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/**
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* @brief ADC notification callback type.
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*
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* @param[in] adcp pointer to the @p ADCDriver object triggering the
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* callback
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* @param[in] buffer pointer to the most recent samples data
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* @param[in] n number of buffer rows available starting from @p buffer
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*/
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typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
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/**
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* @brief ADC error callback type.
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*
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* @param[in] adcp pointer to the @p ADCDriver object triggering the
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* callback
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* @param[in] err ADC error code
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*/
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typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
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/**
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* @brief ADC threshold structure.
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*/
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typedef struct {
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/**
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* @brief ADC channel watchdog mode selection.
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*/
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adcthrhlr_t threshold_mode;
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/**
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* @brief ADC channel selection.
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*/
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uint16_t adc_ch;
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/**
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* @brief ADC channel high threshold value.
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*/
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uint16_t high_threshold_value;
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/**
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* @brief ADC channel low threshold value.
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*/
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uint16_t low_threshold_value;
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} ADCThrhlr;
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/**
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* @brief Conversion group configuration structure.
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* @details This implementation-dependent structure describes a conversion
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* operation.
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* @note Implementations may extend this structure to contain more,
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* architecture dependent, fields.
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*/
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typedef struct {
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/**
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* @brief Enables the circular buffer mode for the group.
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*/
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bool_t circular;
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/**
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* @brief Number of the analog channels belonging to the conversion group.
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*/
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adc_channels_num_t num_channels;
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/**
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* @brief Callback function associated to the group or @p NULL.
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*/
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adccallback_t end_cb;
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/**
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* @brief Error callback or @p NULL.
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*/
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adcerrorcallback_t error_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief ADC Threshold configuration data.
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*/
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#if SPC5_ADC_NTRESHOLD == 4
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ADCThrhlr thresholds[4];
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#elif SPC5_ADC_NTRESHOLD == 16
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ADCThrhlr thresholds[16];
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#endif
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/**
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* @brief ADC CTR0 register initialization data.
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*/
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uint32_t ctr;
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/**
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* @brief Only the conversion of contiguous channels is implemented.
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* Specify initial and final conversion channels.
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*/
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/**
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* @brief ADC Initial conversion channel.
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*/
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uint32_t init_channel;
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} ADCConversionGroup;
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/**
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* @brief Driver configuration structure.
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* @note Empty in this implementation can be ignored.
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*/
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typedef struct {
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uint32_t dummy;
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} ADCConfig;
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/**
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* @brief Structure representing an ADC driver.
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*/
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struct ADCDriver {
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/**
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* @brief Driver state.
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*/
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adcstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const ADCConfig *config;
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/**
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* @brief Current samples buffer pointer or @p NULL.
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*/
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adcsample_t *samples;
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/**
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* @brief Current samples buffer depth or @p 0.
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*/
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size_t depth;
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/**
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* @brief Current conversion group pointer or @p NULL.
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*/
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const ADCConversionGroup *grpp;
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#if ADC_USE_WAIT || defined(__DOXYGEN__)
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/**
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* @brief Waiting thread.
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*/
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thread_reference_t thread;
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#endif
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#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the peripheral.
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*/
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mutex_t mutex;
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#endif /* ADC_USE_MUTUAL_EXCLUSION */
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#if defined(ADC_DRIVER_EXT_FIELDS)
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ADC_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief EDMA channel used for the ADC.
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*/
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edma_channel_t adc_dma_channel;
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/**
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* @brief Pointer to the ADCx registers block.
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*/
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volatile struct spc5_adc *adc_tagp;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if SPC5_ADC_USE_ADC0 && !defined(__DOXYGEN__)
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extern ADCDriver ADCD1;
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#endif
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#if SPC5_ADC_USE_ADC1 && !defined(__DOXYGEN__)
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extern ADCDriver ADCD2;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void adc_lld_init(void);
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void adc_lld_start(ADCDriver *adcp);
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void adc_lld_stop(ADCDriver *adcp);
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void adc_lld_start_conversion(ADCDriver *adcp);
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void adc_lld_stop_conversion(ADCDriver *adcp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_ADC */
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#endif /* _ADC_LLD_H_ */
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/** @} */
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