209 lines
5.6 KiB
ArmAsm
209 lines
5.6 KiB
ArmAsm
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC57EMxx_HSM/boot.s
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* @brief SPC57EMxx_HSM boot-related code.
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*
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* @addtogroup PPC_BOOT
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* @{
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*/
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#include "boot.h"
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#define HSBI_CCR 0xA3F14004
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#define HSBI_CCR_CE 0x00000001
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#define HSBI_CCR_INV 0x00000002
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#if !defined(__DOXYGEN__)
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/* Boot record.*/
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.section .boot, "ax"
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.long 0xFFFF0000
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.long 0xFFFF0000
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.long 0xFFFFFFFF
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.long _reset_address
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.align 2
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.globl _reset_address
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.type _reset_address, @function
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_reset_address:
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bl _coreinit
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bl _ivinit
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b _boot_address
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.align 2
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_coreinit:
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#if 0
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/*
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* Cache invalidate and enable.
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*/
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lis %r7, HSBI_CCR@h
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ori %r7, %r7, HSBI_CCR@l
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li %r0, HSBI_CCR_INV | HSBI_CCR_CE
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stw %r0, 0(%r7)
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.inv:
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lwz %r0, 0(%r7)
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andi. %r0, %r0, HSBI_CCR_INV
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bne+ %cr0, .inv
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#endif
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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*/
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl %cr0, %r4, %r5
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bge %cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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/*
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* Branch prediction enabled.
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*/
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li %r3, BUCSR_DEFAULT
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mtspr 1013, %r3 /* BUCSR */
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blr
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/*
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* Exception vectors initialization.
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*/
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.align 2
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_ivinit:
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/* MSR initialization.*/
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lis %r3, MSR_DEFAULT@h
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ori %r3, %r3, MSR_DEFAULT@l
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mtMSR %r3
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/* IVPR initialization.*/
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lis %r3, __ivpr_base__@h
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ori %r3, %r3, __ivpr_base__@l
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mtIVPR %r3
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blr
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.section .ivors, "ax"
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.globl IVORS
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IVORS:
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IVOR0: b _IVOR0
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.align 4
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IVOR1: b _IVOR1
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.align 4
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IVOR2: b _IVOR2
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.align 4
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IVOR3: b _IVOR3
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.align 4
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IVOR4: b _IVOR4
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.align 4
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IVOR5: b _IVOR5
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.align 4
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IVOR6: b _IVOR6
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.align 4
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IVOR7: b _IVOR7
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.align 4
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IVOR8: b _IVOR8
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.align 4
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IVOR9: b _IVOR9
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.align 4
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IVOR10: b _IVOR10
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.align 4
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IVOR11: b _IVOR11
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.align 4
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IVOR12: b _IVOR12
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.align 4
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IVOR13: b _IVOR13
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.align 4
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IVOR14: b _IVOR14
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.align 4
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IVOR15: b _IVOR15
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.section .handlers, "ax"
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/*
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* Default IVOR handlers.
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*/
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.align 2
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.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
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.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
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.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
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_IVOR0:
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_IVOR1:
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_IVOR2:
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_IVOR3:
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_IVOR5:
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_IVOR6:
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_IVOR7:
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_IVOR8:
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_IVOR9:
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_IVOR11:
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_IVOR12:
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_IVOR13:
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_IVOR14:
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_IVOR15:
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.global _unhandled_exception
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_unhandled_exception:
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b _unhandled_exception
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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