247 lines
7.5 KiB
C
247 lines
7.5 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/adc_lld.c
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* @brief STM32 ADC subsystem low level driver source.
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*
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* @addtogroup STM32_ADC
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if CH_HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief ADC1 driver identifier.*/
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#if USE_STM32_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if USE_STM32_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief ADC1 DMA interrupt handler (channel 1).
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*/
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CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
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uint32_t isr;
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CH_IRQ_PROLOGUE();
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isr = DMA1->ISR;
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DMA1->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
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DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
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if ((isr & DMA_ISR_HTIF1) != 0) {
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/* Half transfer processing.*/
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if (ADCD1.ad_callback != NULL) {
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/* Invokes the callback passing the 1st half of the buffer.*/
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ADCD1.ad_callback(ADCD1.ad_samples, ADCD1.ad_depth / 2);
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}
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}
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if ((isr & DMA_ISR_TCIF1) != 0) {
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/* Transfer complete processing.*/
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if (!ADCD1.ad_grpp->acg_circular) {
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/* End conversion.*/
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adc_lld_stop_conversion(&ADCD1);
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ADCD1.ad_grpp = NULL;
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ADCD1.ad_state = ADC_COMPLETE;
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chSysLockFromIsr();
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chSemResetI(&ADCD1.ad_sem, 0);
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chSysUnlockFromIsr();
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}
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/* Callback handling.*/
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if (ADCD1.ad_callback != NULL) {
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if (ADCD1.ad_depth > 1) {
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/* Invokes the callback passing the 2nd half of the buffer.*/
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size_t half = ADCD1.ad_depth / 2;
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ADCD1.ad_callback(ADCD1.ad_samples + half, half);
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}
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else {
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/* Invokes the callback passing the whole buffer.*/
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ADCD1.ad_callback(ADCD1.ad_samples, ADCD1.ad_depth);
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}
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}
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}
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if ((isr & DMA_ISR_TEIF1) != 0) {
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/* DMA error processing.*/
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STM32_ADC1_DMA_ERROR_HOOK();
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}
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CH_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*/
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void adc_lld_init(void) {
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#if USE_STM32_ADC1
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/* ADC reset, ensures reset state in order to avoid trouble with JTAGs.*/
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RCC->APB2RSTR = RCC_APB2RSTR_ADC1RST;
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RCC->APB2RSTR = 0;
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.ad_adc = ADC1;
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ADCD1.ad_dma = DMA1_Channel1;
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ADCD1.ad_dmaprio = STM32_ADC1_DMA_PRIORITY << 12;
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/* Temporary activation.*/
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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ADC1->CR1 = 0;
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ADC1->CR2 = ADC_CR2_ADON;
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/* Reset calibration just to be safe.*/
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ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
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while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
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;
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/* Calibration.*/
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ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
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while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
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;
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/* Return the ADC in low power mode.*/
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ADC1->CR2 = 0;
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RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
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#endif
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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void adc_lld_start(ADCDriver *adcp) {
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/* If in stopped state then enables the ADC and DMA clocks.*/
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if (adcp->ad_state == ADC_STOP) {
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#if USE_STM32_ADC1
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if (&ADCD1 == adcp) {
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dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
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NVICEnableVector(DMA1_Channel1_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ADC1_IRQ_PRIORITY));
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DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR;
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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}
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#endif
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/* ADC setup, the calibration procedure has already been performed
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during initialization.*/
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adcp->ad_adc->CR1 = ADC_CR1_SCAN;
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adcp->ad_adc->CR2 = 0;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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/* If in ready state then disables the ADC clock.*/
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if (adcp->ad_state == ADC_READY) {
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#if USE_STM32_ADC1
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if (&ADCD1 == adcp) {
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ADC1->CR1 = 0;
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ADC1->CR2 = 0;
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NVICDisableVector(DMA1_Channel1_IRQn);
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dmaDisable(DMA1_ID);
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RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
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}
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#endif
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}
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}
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/**
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* @brief Starts an ADC conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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void adc_lld_start_conversion(ADCDriver *adcp) {
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uint32_t ccr, n;
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const ADCConversionGroup *grpp = adcp->ad_grpp;
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/* DMA setup.*/
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adcp->ad_dma->CMAR = (uint32_t)adcp->ad_samples;
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ccr = adcp->ad_dmaprio | DMA_CCR1_EN | DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0 |
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DMA_CCR1_MINC | DMA_CCR1_TCIE | DMA_CCR1_TEIE;
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if (grpp->acg_circular)
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ccr |= DMA_CCR1_CIRC;
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if (adcp->ad_depth > 1) {
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/* If the buffer depth is greater than one then the half transfer interrupt
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interrupt is enabled in order to allows streaming processing.*/
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ccr |= DMA_CCR1_HTIE;
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n = (uint32_t)grpp->acg_num_channels * (uint32_t)adcp->ad_depth;
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}
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else
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n = (uint32_t)grpp->acg_num_channels;
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adcp->ad_dma->CNDTR = n;
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adcp->ad_dma->CCR = ccr;
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/* ADC setup.*/
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adcp->ad_adc->SMPR1 = grpp->acg_smpr1;
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adcp->ad_adc->SMPR2 = grpp->acg_smpr2;
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adcp->ad_adc->SQR1 = grpp->acg_sqr1;
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adcp->ad_adc->SQR2 = grpp->acg_sqr2;
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adcp->ad_adc->SQR3 = grpp->acg_sqr3;
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adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN;
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adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
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/* ADC start.*/
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adcp->ad_adc->CR2 |= ADC_CR2_SWSTART | ADC_CR2_EXTTRIG;
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}
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/**
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* @brief Stops an ongoing conversion.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*/
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void adc_lld_stop_conversion(ADCDriver *adcp) {
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adcp->ad_dma->CCR = 0;
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adcp->ad_adc->CR2 = 0;
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}
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#endif /* CH_HAL_USE_ADC */
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/** @} */
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