272 lines
9.7 KiB
C
272 lines
9.7 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file IAR/ARMCMx/chcore.h
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* @brief ARM Cortex-Mx port macros and structures.
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*
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* @addtogroup IAR_ARMCMx_CORE
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* @{
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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/*===========================================================================*/
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/* Port constants (common). */
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/*===========================================================================*/
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/* Added to make the header stand-alone when included from asm.*/
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE
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#define TRUE (!FALSE)
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#endif
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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#include "cmparams.h"
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/* Cortex model check, only M0 and M3 supported right now.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3)
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#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4)
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#error "untested Cortex-M model, manually remove this check in chcore.h"
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#else
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#error "unknown or unsupported Cortex-M model"
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#endif
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/**
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* @brief Total priority levels.
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*/
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#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
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/**
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* @brief Minimum priority level.
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* @details This minimum priority level is calculated from the number of
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* priority bits supported by the specific Cortex-Mx implementation.
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*/
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#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
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/**
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* @brief Maximum priority level.
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* @details The maximum allowed priority level is always zero.
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*/
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#define CORTEX_MAXIMUM_PRIORITY 0
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/*===========================================================================*/
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/* Port macros (common). */
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/*===========================================================================*/
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_PRIORITY(n) \
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(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level to priority mask conversion macro.
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*/
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#define CORTEX_PRIORITY_MASK(n) \
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((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* Port configurable parameters (common). */
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/*===========================================================================*/
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p PORT_INT_REQUIRED_STACK.
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* @note In this port it is set to 16 because the idle thread does have
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* a stack frame when compiling without optimizations. You may
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* reduce this value to zero when compiling with optimizations.
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*/
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#ifndef PORT_IDLE_THREAD_STACK_SIZE
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#define PORT_IDLE_THREAD_STACK_SIZE 16
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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* This value can be zero on those architecture where there is a
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* separate interrupt stack and the stack space between @p intctx and
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* @p extctx is known to be zero.
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* @note In this port it is conservatively set to 16 because the function
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* @p chSchDoReschedule() can have a stack frame, expecially with
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* compiler optimizations disabled.
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*/
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#ifndef PORT_INT_REQUIRED_STACK
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#define PORT_INT_REQUIRED_STACK 16
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#endif
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/**
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* @brief Enables the use of the WFI instruction in the idle thread loop.
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*/
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#ifndef CORTEX_ENABLE_WFI_IDLE
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#define CORTEX_ENABLE_WFI_IDLE FALSE
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#endif
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/**
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* @brief SYSTICK handler priority.
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* @note The default SYSTICK handler priority is calculated as the priority
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* level in the middle of the numeric priorities range.
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*/
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#ifndef CORTEX_PRIORITY_SYSTICK
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#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
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#else
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/* If it is externally redefined then better perform a validity check on it.*/
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#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
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#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
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#endif
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#endif
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/**
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* @brief Stack alignment enforcement.
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* @note The default value is 64 in order to comply with EABI, reducing
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* the value to 32 can save some RAM space if you don't care about
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* binary compatibility with EABI compiled libraries.
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* @note Allowed values are 32 or 64.
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*/
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#ifndef CORTEX_STACK_ALIGNMENT
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#define CORTEX_STACK_ALIGNMENT 64
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#endif
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/*===========================================================================*/
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/* Port derived parameters (common). */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port exported info (common). */
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/*===========================================================================*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM
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/**
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* @brief Name of the compiler supported by this port.
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*/
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#define CH_COMPILER_NAME "IAR"
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/*===========================================================================*/
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/* Port implementation part (common). */
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/*===========================================================================*/
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/* Includes the sub-architecture-specific part.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M1)
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#include "chcore_v6m.h"
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#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
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#include "chcore_v7m.h"
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#endif
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#if !defined(_FROM_ASM_)
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#include <intrinsics.h>
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#include "nvic.h"
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/**
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* @brief Stack and memory alignment enforcement.
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*/
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#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__)
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typedef uint64_t stkalign_t;
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#elif CORTEX_STACK_ALIGNMENT == 32
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typedef uint32_t stkalign_t;
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#else
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#error "invalid stack alignment selected"
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#endif
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#if defined(__DOXYGEN__)
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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* @note It is implemented to match the Cortex-Mx exception context.
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*/
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struct extctx {
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/* Dummy definition, just for Doxygen.*/
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};
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switching.
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*/
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struct intctx {
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/* Dummy definition, just for Doxygen.*/
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};
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#endif
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/**
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* @brief Platform dependent part of the @p Thread structure.
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* @details In this port the structure just holds a pointer to the @p intctx
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* structure representing the stack pointer at context switch time.
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*/
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struct context {
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struct intctx *r13;
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};
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/**
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* @brief Platform dependent part of the @p chThdCreateI() API.
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* @details This code usually setup the context switching frame represented
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* by an @p intctx structure.
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*/
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#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
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tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
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wsize - \
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sizeof(struct intctx)); \
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tp->p_ctx.r13->r4 = (void *)pf; \
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tp->p_ctx.r13->r5 = (void *)arg; \
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tp->p_ctx.r13->lr = (void *)_port_thread_start; \
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}
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/**
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* @brief Enforces a correct alignment for a stack area size value.
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*/
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#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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/**
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* @brief Computes the thread working area global size.
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*/
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#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + (PORT_INT_REQUIRED_STACK))
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/**
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* @brief Static working area allocation.
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* @details This macro is used to allocate a static thread working area
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* aligned as both position and size.
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*/
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#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
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#endif /* _FROM_ASM_ */
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#endif /* _CHCORE_H_ */
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/** @} */
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