77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/*
|
|
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
|
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
|
you may not use this file except in compliance with the License.
|
|
You may obtain a copy of the License at
|
|
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
See the License for the specific language governing permissions and
|
|
limitations under the License.
|
|
*/
|
|
|
|
/*
|
|
* STM32F0xx drivers configuration.
|
|
* The following settings override the default settings present in
|
|
* the various device driver implementation headers.
|
|
* Note that the settings for each driver only have effect if the whole
|
|
* driver is enabled in halconf.h.
|
|
*
|
|
* IRQ priorities:
|
|
* 3...0 Lowest...Highest.
|
|
*
|
|
* DMA priorities:
|
|
* 0...3 Lowest...Highest.
|
|
*/
|
|
|
|
#define KL2x_MCUCONF
|
|
|
|
/*
|
|
* HAL driver system settings.
|
|
*/
|
|
|
|
/* Select the MCU clocking mode below by enabling the appropriate block. */
|
|
|
|
/* FEI mode */
|
|
#if 0
|
|
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
|
|
#define KINETIS_SYSCLK_FREQUENCY 21000000UL
|
|
#endif /* 0 */
|
|
|
|
/* FEE mode - 24 MHz with external 32.768 kHz crystal */
|
|
#if 0
|
|
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
|
|
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
|
|
#define KINETIS_MCG_FLL_DRS 0 /* 732x FLL factor */
|
|
#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 24 MHz */
|
|
#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 12 MHz */
|
|
#define KINETIS_SYSCLK_FREQUENCY 23986176UL /* 32.768 kHz*732 (~24 MHz) */
|
|
#define KINETIS_UART0_CLOCK_FREQ (32768 * 732) /* FLL output */
|
|
#define KINETIS_UART0_CLOCK_SRC 1 /* Select FLL clock */
|
|
#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
|
|
#endif /* 0 */
|
|
|
|
/* FEE mode - 48 MHz */
|
|
#if 0
|
|
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEE
|
|
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
|
|
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
|
|
#define KINETIS_MCG_FLL_OUTDIV1 1 /* Divide 48 MHz FLL by 1 => 48 MHz */
|
|
#define KINETIS_MCG_FLL_OUTDIV4 2 /* Divide OUTDIV1 output by 2 => 24 MHz */
|
|
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
|
|
#endif /* 0 */
|
|
|
|
/*
|
|
* SERIAL driver system settings.
|
|
*/
|
|
#define KINETIS_SERIAL_USE_UART0 TRUE
|
|
|
|
/*
|
|
* ADC driver system settings.
|
|
*/
|
|
#define KINETIS_ADC_USE_ADC0 TRUE
|