450 lines
15 KiB
C
450 lines
15 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCMx/chcore.h
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* @brief ARM Cortex-Mx architecture port macros and structures.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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#include "nvic.h"
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/*===========================================================================*/
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/* Port constants. */
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/*===========================================================================*/
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/**
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* @brief Port implementing a process mode context switching.
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* @details This macro can be used to differentiate this port from the other
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* Cortex-Mx port which defines @p CORTEX_PORT_MODE_ENDOSWITCH.
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*/
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#define CORTEX_PORT_MODE_EXOSWITCH
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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#include "cmparams.h"
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/* Cortex model check, only M0 and M3 right now.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3)
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#else
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#error "unknown or unsupported Cortex-M model"
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#endif
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/*===========================================================================*/
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/* Port derived parameters. */
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/*===========================================================================*/
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/**
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* @brief Priority masking support.
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*/
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#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__)
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#define CORTEX_SUPPORTS_BASEPRI TRUE
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#else
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#define CORTEX_SUPPORTS_BASEPRI FALSE
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#endif
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/**
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* @brief Total priority levels.
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*/
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#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
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/**
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* @brief Minimum priority level.
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* @details This minimum priority level is calculated from the number of
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* priority bits supported by the specific Cortex-Mx implementation.
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*/
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#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
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/**
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* @brief Maximum priority level.
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* @details The maximum allowed priority level is always zero.
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*/
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#define CORTEX_MAXIMUM_PRIORITY 0
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/*===========================================================================*/
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/* Port macros. */
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/*===========================================================================*/
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_PRIORITY(n) \
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(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level to priority mask conversion macro.
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*/
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#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* Port configurable parameters. */
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/*===========================================================================*/
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/**
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* @brief Enables the use of the WFI instruction in the idle thread loop.
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*/
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#ifndef CORTEX_ENABLE_WFI_IDLE
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#define CORTEX_ENABLE_WFI_IDLE FALSE
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#endif
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/**
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* @brief SYSTICK handler priority.
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* @note The default is calculated as the priority level in the middle
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* of the priority range.
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*/
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#ifndef CORTEX_PRIORITY_SYSTICK
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#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
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#else
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/* If it is externally redefined then better perform a validity check on it.*/
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#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
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#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
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#endif
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#endif
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/*===========================================================================*/
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/* Port exported info. */
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/*===========================================================================*/
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#if defined(__DOXYGEN__)
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/**
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* @brief Macro defining the ARM architecture.
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*/
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#define CH_ARCHITECTURE_ARM_vxm
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/**
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* @brief Name of the implemented architecture.
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*/
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#define CH_ARCHITECTURE_NAME "ARMvx-M"
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/**
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* @brief Name of the architecture variant (optional).
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*/
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#define CH_CORE_VARIANT_NAME "Cortex-Mx"
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#elif CORTEX_MODEL == CORTEX_M4
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#define CH_ARCHITECTURE_ARM_v7M
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#define CH_ARCHITECTURE_NAME "ARMv7-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M4"
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#elif CORTEX_MODEL == CORTEX_M3
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#define CH_ARCHITECTURE_ARM_v7M
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#define CH_ARCHITECTURE_NAME "ARMv7-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M3"
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#elif CORTEX_MODEL == CORTEX_M1
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#define CH_ARCHITECTURE_ARM_v6M
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#define CH_ARCHITECTURE_NAME "ARMv6-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M1"
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#elif CORTEX_MODEL == CORTEX_M0
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#define CH_ARCHITECTURE_ARM_v6M
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#define CH_ARCHITECTURE_NAME "ARMv6-M"
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#define CH_CORE_VARIANT_NAME "Cortex-M0"
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#endif
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/*===========================================================================*/
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/* Port implementation part. */
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/*===========================================================================*/
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/**
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* @brief 32 bits stack and memory alignment enforcement.
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*/
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typedef uint32_t stkalign_t;
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/**
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* @brief Generic ARM register.
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*/
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typedef void *regarm_t;
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/**
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* @brief Cortex-Mx exception context.
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*/
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struct cmxctx {
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t r12;
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regarm_t lr_thd;
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regarm_t pc;
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regarm_t xpsr;
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};
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#if !defined(__DOXYGEN__)
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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*/
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struct extctx {
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regarm_t xpsr;
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regarm_t r12;
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regarm_t lr;
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regarm_t r0;
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regarm_t r1;
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regarm_t r2;
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regarm_t r3;
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regarm_t pc;
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};
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#endif
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#if !defined(__DOXYGEN__)
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switching.
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*/
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#if defined(CH_ARCHITECTURE_ARM_v6M)
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struct intctx {
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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regarm_t r7;
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regarm_t lr;
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};
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#elif defined(CH_ARCHITECTURE_ARM_v7M)
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struct intctx {
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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regarm_t r7;
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr;
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};
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#endif
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#endif
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#if !defined(__DOXYGEN__)
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/**
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* @brief Platform dependent part of the @p Thread structure.
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* @details In the Cortex-Mx port this structure just holds a pointer to the
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* @p intctx structure representing the stack pointer at the time
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* of the context switch.
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*/
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struct context {
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struct intctx *r13;
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};
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#endif
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/**
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* @brief Platform dependent part of the @p chThdInit() API.
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* @details This code usually setup the context switching frame represented
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* by an @p intctx structure.
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*/
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#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
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tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
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wsize - \
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sizeof(struct intctx)); \
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tp->p_ctx.r13->r4 = pf; \
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tp->p_ctx.r13->r5 = arg; \
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tp->p_ctx.r13->lr = _port_thread_start; \
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}
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p INT_REQUIRED_STACK.
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* @note In this port it is set to 4 because the idle thread does have
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* a stack frame when compiling without optimizations.
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*/
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#ifndef IDLE_THREAD_STACK_SIZE
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#define IDLE_THREAD_STACK_SIZE 4
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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* This value can be zero on those architecture where there is a
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* separate interrupt stack and the stack space between @p intctx and
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* @p extctx is known to be zero.
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* @note This port requires some extra stack space for interrupt handling
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* representing the frame of the function @p chSchDoRescheduleI().
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*/
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#ifndef INT_REQUIRED_STACK
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#define INT_REQUIRED_STACK 8
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#endif
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/**
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* @brief Enforces a correct alignment for a stack area size value.
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*/
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#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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/**
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* @brief Computes the thread working area global size.
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*/
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#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + (INT_REQUIRED_STACK))
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/**
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* @brief Static working area allocation.
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* @details This macro is used to allocate a static thread working area
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* aligned as both position and size.
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*/
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#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)];
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/**
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* @brief IRQ prologue code.
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* @details This macro must be inserted at the start of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_PROLOGUE() { \
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chSysLockFromIsr(); \
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_port_irq_nesting++; \
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chSysUnlockFromIsr(); \
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}
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/**
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* @brief IRQ epilogue code.
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* @details This macro must be inserted at the end of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_EPILOGUE() { \
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chSysLockFromIsr(); \
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if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \
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register struct cmxctx *ctxp asm ("r3"); \
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\
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asm volatile ("mrs %0, PSP" : "=r" (ctxp) : "r" (ctxp)); \
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_port_saved_pc = ctxp->pc; \
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ctxp->pc = _port_switch_from_irq; \
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return; \
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} \
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chSysUnlockFromIsr(); \
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}
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/**
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* @brief IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#define PORT_IRQ_HANDLER(id) void id(void)
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/**
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* @brief Port-related initialization code.
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*/
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#define port_init() { \
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_port_irq_nesting = 0; \
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
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CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
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}
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/**
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* @brief Kernel-lock action.
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* @details Usually this function just disables interrupts but may perform
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* more actions.
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* @note In this port it disables all the interrupt sources.
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*/
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#define port_lock() asm volatile ("cpsid i")
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/**
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* @brief Kernel-unlock action.
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* @details Usually this function just disables interrupts but may perform
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* more actions.
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* @note In this port it enables all the interrupt sources.
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*/
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#define port_unlock() asm volatile ("cpsie i")
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/**
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* @brief Kernel-lock action from an interrupt handler.
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* @details This function is invoked before invoking I-class APIs from
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* interrupt handlers. The implementation is architecture dependent,
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* in its simplest form it is void.
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* @note Same as @p port_lock() in this port.
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*/
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#define port_lock_from_isr() port_lock()
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/**
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* @brief Kernel-unlock action from an interrupt handler.
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* @details This function is invoked after invoking I-class APIs from interrupt
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* handlers. The implementation is architecture dependent, in its
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* simplest form it is void.
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* @note Same as @p port_unlock() in this port.
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*/
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#define port_unlock_from_isr() port_unlock()
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/**
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* @brief Disables all the interrupt sources.
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* @note Of course non maskable interrupt sources are not included.
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* @note In this port it disables all the interrupt sources.
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*/
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#define port_disable() asm volatile ("cpsid i")
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/**
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* @brief Disables the interrupt sources below kernel-level priority.
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* @note Interrupt sources above kernel level remains enabled.
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* @note In this port it disables all the interrupt sources.
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*/
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#define port_suspend() asm volatile ("cpsid i")
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/**
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* @brief Enables all the interrupt sources.
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* @note In this port it enables all the interrupt sources.
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*/
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#define port_enable() asm volatile ("cpsie i")
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/**
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* @brief Enters an architecture-dependent IRQ-waiting mode.
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* @details The function is meant to return when an interrupt becomes pending.
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* The simplest implementation is an empty function or macro but this
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* would not take advantage of architecture-specific power saving
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* modes.
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* @note Implemented as an inlined @p WFI instruction.
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*/
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#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
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#define port_wait_for_interrupt() asm volatile ("wfi")
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#else
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#define port_wait_for_interrupt()
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#endif
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#if !defined(__DOXYGEN__)
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extern regarm_t _port_saved_pc;
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extern unsigned _port_irq_nesting;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void port_halt(void);
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void port_switch(Thread *ntp, Thread *otp);
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void _port_switch_from_irq(void);
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void _port_thread_start(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _CHCORE_H_ */
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/** @} */
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