1991 lines
88 KiB
C
1991 lines
88 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F0xx/stm32_registry.h
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* @brief STM32F0xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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#if !defined(STM32F0XX) || defined(__DOXYGEN__)
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#define STM32F0XX
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F0xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* STM32F051x8, STM32F058xx. */
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/*===========================================================================*/
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#if defined(STM32F051x8) || defined(STM32F058xx) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC_SUPPORTS_PRESCALER FALSE
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#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
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#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
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#define STM32_ADC1_HANDLER Vector70
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#define STM32_ADC1_NUMBER 12
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_DAC1_CH1_DMA_CHN 0x00000000
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#define STM32_HAS_DAC1_CH2 FALSE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 5
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#define STM32_DMA2_NUM_CHANNELS 0
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#define STM32_DMA1_CH1_HANDLER Vector64
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#define STM32_DMA1_CH23_HANDLER Vector68
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#define STM32_DMA1_CH4567_HANDLER Vector6C
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#define STM32_DMA1_CH1_NUMBER 9
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#define STM32_DMA1_CH23_NUMBER 10
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#define STM32_DMA1_CH4567_NUMBER 11
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#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
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#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
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#define DMA1_CH2_CMASK 0x00000006U
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#define DMA1_CH3_CMASK 0x00000006U
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#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
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#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
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#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
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#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
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#define DMA1_CH4_CMASK 0x00000078U
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#define DMA1_CH5_CMASK 0x00000078U
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#define DMA1_CH6_CMASK 0x00000078U
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#define DMA1_CH7_CMASK 0x00000078U
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 32
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#define STM32_EXTI_IMR_MASK 0x0F940000U
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
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#define STM32_RTC_NUM_ALARMS 1
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_SPI1_RX_DMA_CHN 0x00000000
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#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00000000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_USART2_RX_DMA_CHN 0x00000000
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#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_USART2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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/*===========================================================================*/
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/* STM32F071xB, STM32F072xB, STM32F078xx. */
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/*===========================================================================*/
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#elif defined(STM32F071xB) || defined(STM32F072xB) || \
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defined(STM32F078xx)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC_SUPPORTS_PRESCALER FALSE
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#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
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#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
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#define STM32_ADC1_HANDLER Vector70
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#define STM32_ADC1_NUMBER 12
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#if defined(STM32F072xB)
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#define STM32_HAS_CAN1 TRUE
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#define STM32_CAN_MAX_FILTERS 14
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#else
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#define STM32_HAS_CAN1 FALSE
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#endif
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#define STM32_HAS_CAN2 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_DAC1_CH1_DMA_CHN 0x00000000
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_DAC1_CH2_DMA_CHN 0x00000000
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA2_NUM_CHANNELS 0
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#define STM32_DMA1_CH1_HANDLER Vector64
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#define STM32_DMA1_CH23_HANDLER Vector68
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#define STM32_DMA1_CH4567_HANDLER Vector6C
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#define STM32_DMA1_CH1_NUMBER 9
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#define STM32_DMA1_CH23_NUMBER 10
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#define STM32_DMA1_CH4567_NUMBER 11
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#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
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#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
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#define DMA1_CH2_CMASK 0x00000006U
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#define DMA1_CH3_CMASK 0x00000006U
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#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
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#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
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#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
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#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
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#define DMA1_CH4_CMASK 0x00000078U
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#define DMA1_CH5_CMASK 0x00000078U
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#define DMA1_CH6_CMASK 0x00000078U
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#define DMA1_CH7_CMASK 0x00000078U
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 32
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#define STM32_EXTI_IMR_MASK 0x7F840000U
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | \
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RCC_AHBENR_GPIOFEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
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#define STM32_RTC_NUM_ALARMS 1
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_SPI1_RX_DMA_CHN 0x00000000
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#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
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STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
|
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#if defined(STM32F072xB) || defined(STM32F078xx)
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
|
#define STM32_USB_PMA_SIZE 768
|
|
#define STM32_USB_HAS_BCDR TRUE
|
|
#else
|
|
#define STM32_HAS_USB FALSE
|
|
#endif
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F048xx. */
|
|
/*===========================================================================*/
|
|
#elif defined(STM32F048xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC_SUPPORTS_PRESCALER FALSE
|
|
#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
|
|
#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
|
|
#define STM32_ADC1_HANDLER Vector70
|
|
#define STM32_ADC1_NUMBER 12
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
#define STM32_DMA1_NUM_CHANNELS 5
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
#define STM32_DMA1_CH1_HANDLER Vector64
|
|
#define STM32_DMA1_CH23_HANDLER Vector68
|
|
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_NUMBER 9
|
|
#define STM32_DMA1_CH23_NUMBER 10
|
|
#define STM32_DMA1_CH4567_NUMBER 11
|
|
|
|
#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define DMA1_CH2_CMASK 0x00000006U
|
|
#define DMA1_CH3_CMASK 0x00000006U
|
|
|
|
#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define DMA1_CH4_CMASK 0x00000078U
|
|
#define DMA1_CH5_CMASK 0x00000078U
|
|
#define DMA1_CH6_CMASK 0x00000078U
|
|
#define DMA1_CH7_CMASK 0x00000078U
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 32
|
|
#define STM32_EXTI_IMR_MASK 0x7FF40000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD FALSE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
|
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_I2C2 FALSE
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM6 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART3 FALSE
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
|
#define STM32_USB_PMA_SIZE 768
|
|
#define STM32_USB_HAS_BCDR TRUE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F031x6, STM32F038xx. */
|
|
/*===========================================================================*/
|
|
#elif defined(STM32F031x6) || defined(STM32F038xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC_SUPPORTS_PRESCALER FALSE
|
|
#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
|
|
#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
|
|
#define STM32_ADC1_HANDLER Vector70
|
|
#define STM32_ADC1_NUMBER 12
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
#define STM32_DMA1_NUM_CHANNELS 5
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
#define STM32_DMA1_CH1_HANDLER Vector64
|
|
#define STM32_DMA1_CH23_HANDLER Vector68
|
|
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_NUMBER 9
|
|
#define STM32_DMA1_CH23_NUMBER 10
|
|
#define STM32_DMA1_CH4567_NUMBER 11
|
|
|
|
#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define DMA1_CH2_CMASK 0x00000006U
|
|
#define DMA1_CH3_CMASK 0x00000006U
|
|
|
|
#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define DMA1_CH4_CMASK 0x00000078U
|
|
#define DMA1_CH5_CMASK 0x00000078U
|
|
#define DMA1_CH6_CMASK 0x00000078U
|
|
#define DMA1_CH7_CMASK 0x00000078U
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 32
|
|
#define STM32_EXTI_IMR_MASK 0x0FF40000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD FALSE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
|
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_I2C2 FALSE
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI2 FALSE
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM6 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART2 FALSE
|
|
#define STM32_HAS_USART3 FALSE
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F042x6. */
|
|
/*===========================================================================*/
|
|
#elif defined(STM32F042x6)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC_SUPPORTS_PRESCALER FALSE
|
|
#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
|
|
#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
|
|
#define STM32_ADC1_HANDLER Vector70
|
|
#define STM32_ADC1_NUMBER 12
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
#define STM32_DMA1_NUM_CHANNELS 5
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
#define STM32_DMA1_CH1_HANDLER Vector64
|
|
#define STM32_DMA1_CH23_HANDLER Vector68
|
|
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_NUMBER 9
|
|
#define STM32_DMA1_CH23_NUMBER 10
|
|
#define STM32_DMA1_CH4567_NUMBER 11
|
|
|
|
#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define DMA1_CH2_CMASK 0x00000006U
|
|
#define DMA1_CH3_CMASK 0x00000006U
|
|
|
|
#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define DMA1_CH4_CMASK 0x00000078U
|
|
#define DMA1_CH5_CMASK 0x00000078U
|
|
#define DMA1_CH6_CMASK 0x00000078U
|
|
#define DMA1_CH7_CMASK 0x00000078U
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 32
|
|
#define STM32_EXTI_IMR_MASK 0x7FF40000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD FALSE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
|
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_I2C2 FALSE
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI2 FALSE
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM6 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM15 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART3 FALSE
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
|
#define STM32_USB_PMA_SIZE 768
|
|
#define STM32_USB_HAS_BCDR TRUE
|
|
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F030x6, STM32F030x8, STM32F030xC. */
|
|
/*===========================================================================*/
|
|
#elif defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F030xC)
|
|
|
|
/* Common identifier of all STM32F030 devices.*/
|
|
#define STM32F030
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC_SUPPORTS_PRESCALER FALSE
|
|
#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
|
|
#define STM32_ADC1_IRQ_SHARED_WITH_EXTI FALSE
|
|
#define STM32_ADC1_HANDLER Vector70
|
|
#define STM32_ADC1_NUMBER 12
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_ADC1_DMA_CHN 0x00000011
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#if defined(STM32F030xC) || defined(__DOXYGEN__)
|
|
#define STM32_DMA_SUPPORTS_CSELR TRUE
|
|
#else
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
#endif
|
|
#define STM32_DMA1_NUM_CHANNELS 5
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
#define STM32_DMA1_CH1_HANDLER Vector64
|
|
#define STM32_DMA1_CH23_HANDLER Vector68
|
|
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_NUMBER 9
|
|
#define STM32_DMA1_CH23_NUMBER 10
|
|
#define STM32_DMA1_CH4567_NUMBER 11
|
|
|
|
#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define DMA1_CH2_CMASK 0x00000006U
|
|
#define DMA1_CH3_CMASK 0x00000006U
|
|
|
|
#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define DMA1_CH4_CMASK 0x00000078U
|
|
#define DMA1_CH5_CMASK 0x00000078U
|
|
#define DMA1_CH6_CMASK 0x00000078U
|
|
#define DMA1_CH7_CMASK 0x00000078U
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 20
|
|
#define STM32_EXTI_IMR_MASK 0xFFF50000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#if defined(STM32F030x8)
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#else
|
|
#define STM32_HAS_GPIOD FALSE
|
|
#endif
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#if defined(STM32F030x8)
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
#else
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
#endif
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00000200
|
|
#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_I2C1_TX_DMA_CHN 0x00000020
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00020000
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x00002000
|
|
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000030
|
|
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00000300
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00003000
|
|
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00030000
|
|
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM2 FALSE
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00080808
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART1_TX_DMA_CHN 0x00008080
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART2_RX_DMA_CHN 0x00090909
|
|
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART2_TX_DMA_CHN 0x00009090
|
|
|
|
#if defined(STM32F030xC)
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART3_RX_DMA_CHN 0x000A0A0A
|
|
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART3_TX_DMA_CHN 0x0000A0A0
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_UART4_RX_DMA_CHN 0x000B0B0B
|
|
#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_UART4_TX_DMA_CHN 0x0000B0B0
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_UART5_RX_DMA_CHN 0x000C0C0C
|
|
#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_UART5_TX_DMA_CHN 0x0000C0C0
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART6_RX_DMA_CHN 0x000D0D0D
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART6_TX_DMA_CHN 0x0000D0D0
|
|
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#else
|
|
#define STM32_HAS_USART3 FALSE
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
#endif
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F070x6, STM32F070xB. */
|
|
/*===========================================================================*/
|
|
#elif defined(STM32F070x6) || defined(STM32F070xB)
|
|
|
|
/* Common identifier of all STM32F070 devices.*/
|
|
#define STM32F070
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC_SUPPORTS_PRESCALER FALSE
|
|
#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
|
|
#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
|
|
#define STM32_ADC1_HANDLER Vector70
|
|
#define STM32_ADC1_NUMBER 12
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2))
|
|
#define STM32_ADC1_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 FALSE
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
#define STM32_DMA1_NUM_CHANNELS 5
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
#define STM32_DMA1_CH1_HANDLER Vector64
|
|
#define STM32_DMA1_CH23_HANDLER Vector68
|
|
#define STM32_DMA1_CH4567_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_NUMBER 9
|
|
#define STM32_DMA1_CH23_NUMBER 10
|
|
#define STM32_DMA1_CH4567_NUMBER 11
|
|
|
|
#define STM32_DMA1_CH2_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define STM32_DMA1_CH3_NUMBER STM32_DMA1_CH23_NUMBER
|
|
#define DMA1_CH2_CMASK 0x00000006U
|
|
#define DMA1_CH3_CMASK 0x00000006U
|
|
|
|
#define STM32_DMA1_CH4_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH5_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH6_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define STM32_DMA1_CH7_NUMBER STM32_DMA1_CH4567_NUMBER
|
|
#define DMA1_CH4_CMASK 0x00000078U
|
|
#define DMA1_CH5_CMASK 0x00000078U
|
|
#define DMA1_CH6_CMASK 0x00000078U
|
|
#define DMA1_CH7_CMASK 0x00000078U
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 32
|
|
#define STM32_EXTI_IMR_MASK 0x7F840000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
|
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM2 FALSE
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4))
|
|
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
|
#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
|
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
|
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
|
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
#define STM32_HAS_UART7 FALSE
|
|
#define STM32_HAS_UART8 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
|
#define STM32_USB_PMA_SIZE 768
|
|
#define STM32_USB_HAS_BCDR TRUE
|
|
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE FALSE
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F091xC, STM32F098xx. */
|
|
/*===========================================================================*/
|
|
#elif defined(STM32F091xC) || defined(STM32F098xx)
|
|
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_ADC_SUPPORTS_PRESCALER FALSE
|
|
#define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE
|
|
#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
|
|
#define STM32_ADC1_HANDLER Vector70
|
|
#define STM32_ADC1_NUMBER 12
|
|
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(3, 5))
|
|
#define STM32_ADC1_DMA_CHN 0x00100011
|
|
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
#define STM32_HAS_CAN2 FALSE
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_DAC1_CH1_DMA_CHN 0x00000100
|
|
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_DAC1_CH2_DMA_CHN 0x00001000
|
|
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_SUPPORTS_CSELR TRUE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA2_NUM_CHANNELS 5
|
|
|
|
#define STM32_DMA1_CH1_HANDLER Vector64
|
|
#define STM32_DMA12_CH23_CH12_HANDLER Vector68
|
|
#define STM32_DMA12_CH4567_CH345_HANDLER Vector6C
|
|
#define STM32_DMA1_CH1_NUMBER 9
|
|
#define STM32_DMA12_CH23_CH12_NUMBER 10
|
|
#define STM32_DMA12_CH4567_CH345_NUMBER 11
|
|
|
|
#define STM32_DMA1_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
|
|
#define STM32_DMA1_CH3_NUMBER STM32_DMA12_CH23_CH12_NUMBER
|
|
#define STM32_DMA2_CH1_NUMBER STM32_DMA12_CH23_CH12_NUMBER
|
|
#define STM32_DMA2_CH2_NUMBER STM32_DMA12_CH23_CH12_NUMBER
|
|
#define DMA1_CH2_CMASK 0x00000186U
|
|
#define DMA1_CH3_CMASK 0x00000186U
|
|
#define DMA2_CH1_CMASK 0x00000186U
|
|
#define DMA2_CH2_CMASK 0x00000186U
|
|
|
|
#define STM32_DMA1_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define STM32_DMA1_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define STM32_DMA1_CH6_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define STM32_DMA1_CH7_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define STM32_DMA2_CH3_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define STM32_DMA2_CH4_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define STM32_DMA2_CH5_NUMBER STM32_DMA12_CH4567_CH345_NUMBER
|
|
#define DMA1_CH4_CMASK 0x00000E78U
|
|
#define DMA1_CH5_CMASK 0x00000E78U
|
|
#define DMA1_CH6_CMASK 0x00000E78U
|
|
#define DMA1_CH7_CMASK 0x00000E78U
|
|
#define DMA2_CH3_CMASK 0x00000E78U
|
|
#define DMA2_CH4_CMASK 0x00000E78U
|
|
#define DMA2_CH5_CMASK 0x00000E78U
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 32
|
|
#define STM32_EXTI_IMR_MASK 0x7F840000U
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7))
|
|
#define STM32_I2C1_RX_DMA_CHN 0x02000200
|
|
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_I2C1_TX_DMA_CHN 0x00200002
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
|
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
|
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
|
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
|
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3))
|
|
#define STM32_SPI1_RX_DMA_CHN 0x00000330
|
|
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4))
|
|
#define STM32_SPI1_TX_DMA_CHN 0x00003300
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6))
|
|
#define STM32_SPI2_RX_DMA_CHN 0x00303000
|
|
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5))
|
|
#define STM32_SPI2_TX_DMA_CHN 0x03030000
|
|
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_USART1_RX_DMA_CHN 0x00880888
|
|
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART1_TX_DMA_CHN 0x08088088
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_USART2_RX_DMA_CHN 0x00990999
|
|
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART2_TX_DMA_CHN 0x09099099
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_USART3_RX_DMA_CHN 0x00AA0AAA
|
|
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART3_TX_DMA_CHN 0x0A0AA0AA
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_UART4_RX_DMA_CHN 0x00BB0BBB
|
|
#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_UART4_TX_DMA_CHN 0x0B0BB0BB
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_UART5_RX_DMA_CHN 0x00CC0CCC
|
|
#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_UART5_TX_DMA_CHN 0x0C0CC0CC
|
|
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_USART6_RX_DMA_CHN 0x00DD0DDD
|
|
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_USART6_TX_DMA_CHN 0x0D0DD0DD
|
|
|
|
#define STM32_HAS_UART7 TRUE
|
|
#define STM32_UART7_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_UART7_RX_DMA_CHN 0x00EE0EEE
|
|
#define STM32_UART7_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_UART7_TX_DMA_CHN 0x0E0EE0EE
|
|
|
|
#define STM32_HAS_UART8 TRUE
|
|
#define STM32_UART8_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 3) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 6) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 3)))
|
|
#define STM32_UART8_RX_DMA_CHN 0x00FF0FFF
|
|
#define STM32_UART8_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
|
STM32_DMA_STREAM_ID_MSK(2, 5))
|
|
#define STM32_UART8_TX_DMA_CHN 0x0F0FF0FF
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
|
|
#else
|
|
#error "STM32F0xx device not specified"
|
|
#endif
|
|
|
|
/** @} */
|
|
|
|
#endif /* _STM32_REGISTRY_H_ */
|
|
|
|
/** @} */
|