158 lines
4.9 KiB
C
158 lines
4.9 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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/*
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* Maximum speed SPI configuration.
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*/
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static const SPIConfig hs_spicfg = {
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NULL,
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0,
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0,
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SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) |
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SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */
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SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */
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};
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/*
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* Low speed SPI configuration.
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*/
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static const SPIConfig ls_spicfg = {
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NULL,
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0,
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0,
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SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) |
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SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */
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SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */
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};
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/*
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* SPI TX and RX buffers.
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*/
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static uint8_t txbuf[512];
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static uint8_t rxbuf[512];
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/*
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* SPI bus contender 1.
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*/
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static WORKING_AREA(spi_thread_1_wa, 256);
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static msg_t spi_thread_1(void *p) {
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(void)p;
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chRegSetThreadName("SPI thread 1");
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while (TRUE) {
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spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */
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palClearPad(PORT_E, PE_LED1); /* LED ON. */
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spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */
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spiSelect(&SPID1); /* Slave Select assertion. */
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spiExchange(&SPID1, 512,
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txbuf, rxbuf); /* Atomic transfer operations. */
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spiUnselect(&SPID1); /* Slave Select de-assertion. */
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spiReleaseBus(&SPID1); /* Ownership release. */
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}
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return 0;
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}
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/*
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* SPI bus contender 2.
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*/
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static WORKING_AREA(spi_thread_2_wa, 256);
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static msg_t spi_thread_2(void *p) {
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(void)p;
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chRegSetThreadName("SPI thread 2");
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while (TRUE) {
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spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */
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palSetPad(PORT_E, PE_LED1); /* LED OFF. */
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spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */
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spiSelect(&SPID1); /* Slave Select assertion. */
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spiExchange(&SPID1, 512,
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txbuf, rxbuf); /* Atomic transfer operations. */
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spiUnselect(&SPID1); /* Slave Select de-assertion. */
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spiReleaseBus(&SPID1); /* Ownership release. */
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}
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return 0;
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}
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/*
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* Application entry point.
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*/
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int main(void) {
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unsigned i;
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/*
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* System initializations.
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* - HAL initialization, this also initializes the configured device drivers
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* and performs the board-specific initializations.
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* - Kernel initialization, the main() function becomes a thread and the
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* RTOS is active.
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*/
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halInit();
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chSysInit();
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/*
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* Prepare transmit pattern.
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*/
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for (i = 0; i < sizeof(txbuf); i++)
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txbuf[i] = (uint8_t)i;
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/* Starting driver for test, DSPI_1 I/O pins setup.*/
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spiStart(&SPID1, &ls_spicfg);
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SIU.PCR[14].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
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SIU.PCR[13].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
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SIU.PCR[15].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */
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SIU.PCR[28].R = PAL_MODE_OUTPUT_ALTERNATE(3); /* CS[1] */
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/* Testing sending and receiving at the same time.*/
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spiExchange(&SPID1, 4, txbuf, rxbuf);
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spiExchange(&SPID1, 32, txbuf, rxbuf);
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spiExchange(&SPID1, 512, txbuf, rxbuf);
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/* Testing clock pulses without data buffering.*/
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spiIgnore(&SPID1, 4);
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spiIgnore(&SPID1, 32);
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/* Testing sending data ignoring incoming data.*/
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spiSend(&SPID1, 4, txbuf);
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spiSend(&SPID1, 32, txbuf);
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/* Testing receiving data while sending idle bits (high level).*/
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spiReceive(&SPID1, 4, rxbuf);
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spiReceive(&SPID1, 32, rxbuf);
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/* Testing stop procedure.*/
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spiStop(&SPID1);
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/*
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* Starting the transmitter and receiver threads.
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*/
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chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa),
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NORMALPRIO + 1, spi_thread_1, NULL);
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chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa),
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NORMALPRIO + 1, spi_thread_2, NULL);
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/*
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* Normal main() thread activity, in this demo it does nothing.
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*/
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while (TRUE) {
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chThdSleepMilliseconds(500);
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palTogglePad(PORT_E, PE_LED2);
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}
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return 0;
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}
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