202 lines
6.8 KiB
C
202 lines
6.8 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file ARMCMx/nilcore.h
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* @brief ARM Cortex-Mx port macros and structures.
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*
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* @addtogroup ARMCMx_CORE
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* @{
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*/
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#ifndef _NILCORE_H_
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#define _NILCORE_H_
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/*===========================================================================*/
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/* Module constants. */
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/*===========================================================================*/
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/**
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* @name Architecture and Compiler
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* @{
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*/
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/**
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* @brief Macro defining a generic ARM architecture.
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*/
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#define PORT_ARCHITECTURE_ARM
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/**
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* @brief Compiler name and version.
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*/
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#if defined(__GNUC__) || defined(__DOXYGEN__)
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#define PORT_COMPILER_NAME "GCC " __VERSION__
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#elif defined(__ICCARM__)
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#define PORT_COMPILER_NAME "IAR"
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#elif defined(__CC_ARM)
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#define PORT_COMPILER_NAME "RVCT"
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#else
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#error "unsupported compiler"
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#endif
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/** @} */
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/**
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* @name Cortex-M variants
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* @{
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*/
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#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
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#define CORTEX_M0PLUS 1 /**< @brief Cortex-M0+ variant. */
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#define CORTEX_M1 2 /**< @brief Cortex-M1 variant. */
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#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
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#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
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/** @} */
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/* Inclusion of the Cortex-Mx implementation specific parameters.*/
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#include "cmparams.h"
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/*===========================================================================*/
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/* Module pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/*
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* Inclusion of the appropriate CMSIS header for the selected device.
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*/
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#if CORTEX_MODEL == CORTEX_M0
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#include "core_cm0.h"
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#elif CORTEX_MODEL == CORTEX_M0PLUS
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#include "core_cm0plus.h"
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#elif CORTEX_MODEL == CORTEX_M3
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#include "core_cm3.h"
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#elif CORTEX_MODEL == CORTEX_M4
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#include "core_cm4.h"
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#else
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#error "unknown or unsupported Cortex-M model"
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#endif
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#endif /* !defined(_FROM_ASM_) */
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/*===========================================================================*/
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/* Module data structures and types. */
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/*===========================================================================*/
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/* The following code is not processed when the file is included from an
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asm module.*/
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#if !defined(_FROM_ASM_)
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/* The following declarations are there just for Doxygen documentation, the
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real declarations are inside the sub-headers being specific for the
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sub-architectures.*/
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#if defined(__DOXYGEN__)
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/**
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* @brief Stack and memory alignment enforcement.
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* @note In this architecture the stack alignment is enforced to 64 bits,
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* 32 bits alignment is supported by hardware but deprecated by ARM,
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* the implementation choice is to not offer the option.
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*/
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typedef uint64_t stkalign_t;
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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* @note It is implemented to match the Cortex-Mx exception context.
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*/
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struct port_extctx {};
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switching.
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*/
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struct port_intctx {};
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#endif /* defined(__DOXYGEN__) */
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#endif /* !defined(_FROM_ASM_) */
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/*===========================================================================*/
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/* Module macros. */
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/*===========================================================================*/
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/**
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* @brief Total priority levels.
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*/
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#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
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/**
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* @brief Minimum priority level.
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* @details This minimum priority level is calculated from the number of
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* priority bits supported by the specific Cortex-Mx implementation.
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*/
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#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
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/**
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* @brief Maximum priority level.
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* @details The maximum allowed priority level is always zero.
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*/
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#define CORTEX_MAXIMUM_PRIORITY 0
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_PRIORITY(n) \
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(((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level verification macro.
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*/
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#define CORTEX_IS_VALID_KERNEL_PRIORITY(n) \
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(((n) >= CORTEX_MAX_KERNEL_PRIORITY) && ((n) < CORTEX_PRIORITY_LEVELS))
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/**
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* @brief Priority level to priority mask conversion macro.
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*/
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#define CORTEX_PRIO_MASK(n) \
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((n) << (8 - CORTEX_PRIORITY_BITS))
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Module inline functions. */
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/*===========================================================================*/
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/* Includes the sub-architecture-specific part.*/
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#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) || \
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(CORTEX_MODEL == CORTEX_M1)
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#include "nilcore_v6m.h"
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#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)
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#include "nilcore_v7m.h"
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#endif
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#endif /* _NILCORE_H_ */
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/** @} */
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