575 lines
18 KiB
C
575 lines
18 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @defgroup STM32F100_HAL STM32F100 HAL Support
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* @details HAL support for STM32 Value Line LD, MD and HD sub-families.
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*
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* @ingroup HAL
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*/
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/**
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* @file STM32F1xx/hal_lld_f100.h
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* @brief STM32F100 Value Line HAL subsystem low level driver header.
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*
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* @addtogroup STM32F100_HAL
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* @{
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*/
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#ifndef _HAL_LLD_F100_H_
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#define _HAL_LLD_F100_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Maximum system clock frequency.
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*/
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#define STM32_SYSCLK_MAX 24000000
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/**
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* @brief Maximum HSE clock frequency.
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*/
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#define STM32_HSECLK_MAX 24000000
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/**
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* @brief Minimum HSE clock frequency.
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*/
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#define STM32_HSECLK_MIN 1000000
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/**
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* @brief Maximum LSE clock frequency.
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*/
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#define STM32_LSECLK_MAX 1000000
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/**
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* @brief Minimum LSE clock frequency.
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*/
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#define STM32_LSECLK_MIN 32768
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/**
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* @brief Maximum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MAX 24000000
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/**
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* @brief Maximum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MIN 1000000
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/**
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* @brief Maximum PLL output clock frequency.
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*/
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#define STM32_PLLOUT_MAX 24000000
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/**
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* @brief Maximum PLL output clock frequency.
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*/
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#define STM32_PLLOUT_MIN 16000000
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/**
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* @brief Maximum APB1 clock frequency.
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*/
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#define STM32_PCLK1_MAX 24000000
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/**
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* @brief Maximum APB2 clock frequency.
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*/
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#define STM32_PCLK2_MAX 24000000
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/**
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* @brief Maximum ADC clock frequency.
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*/
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#define STM32_ADCCLK_MAX 12000000
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/** @} */
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/**
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* @name RCC_CFGR register bits definitions
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* @{
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*/
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#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
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#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
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#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
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#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
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#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
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#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
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#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
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#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
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/** @} */
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/**
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* @name RCC_BDCR register bits definitions
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* @{
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*/
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#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
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#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
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#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
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#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
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#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
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RTC clock. */
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Main clock source selection.
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* @note If the selected clock source is not the PLL then the PLL is not
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* initialized and started.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_SW) || defined(__DOXYGEN__)
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#define STM32_SW STM32_SW_PLL
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#endif
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/**
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* @brief Clock source for the PLL.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#endif
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/**
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* @brief Crystal PLL pre-divider.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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#endif
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/**
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* @brief PLL multiplier value.
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* @note The allowed range is 2...16.
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* @note The default value is calculated for a 24MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLMUL_VALUE 3
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#endif
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/**
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* @brief AHB prescaler value.
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* @note The default value is calculated for a 24MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
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#define STM32_HPRE STM32_HPRE_DIV1
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#endif
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/**
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* @brief APB1 prescaler value.
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*/
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#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
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#define STM32_PPRE1 STM32_PPRE1_DIV1
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#endif
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/**
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* @brief APB2 prescaler value.
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*/
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#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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#endif
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/**
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* @brief ADC prescaler value.
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*/
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#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADCPRE STM32_ADCPRE_DIV2
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#endif
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/**
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* @brief MCO pin setting.
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*/
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#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#endif
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/**
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* @brief RTC clock source.
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*/
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#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
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#define STM32_RTCSEL STM32_RTCSEL_LSI
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*
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* Configuration-related checks.
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*/
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#if !defined(STM32F100_MCUCONF)
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#error "Using a wrong mcuconf.h file, STM32F100_MCUCONF not defined"
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#endif
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/*
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* HSI related checks.
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*/
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#if STM32_HSI_ENABLED
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#else /* !STM32_HSI_ENABLED */
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#if STM32_SW == STM32_SW_HSI
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#error "HSI not enabled, required by STM32_SW"
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#endif
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#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
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#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
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#endif
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#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
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((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
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(STM32_PLLSRC == STM32_PLLSRC_HSI))
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#error "HSI not enabled, required by STM32_MCOSEL"
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#endif
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#endif /* !STM32_HSI_ENABLED */
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/*
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* HSE related checks.
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*/
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#if STM32_HSE_ENABLED
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#if STM32_HSECLK == 0
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#error "HSE frequency not defined"
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#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
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#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
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#endif
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#else /* !STM32_HSE_ENABLED */
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#if STM32_SW == STM32_SW_HSE
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#error "HSE not enabled, required by STM32_SW"
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#endif
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#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
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#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
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#endif
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#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
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((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
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#error "HSE not enabled, required by STM32_MCOSEL"
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#endif
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#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
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#error "HSE not enabled, required by STM32_RTCSELSEL"
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#endif
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#endif /* !STM32_HSE_ENABLED */
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/*
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* LSI related checks.
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*/
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#if STM32_LSI_ENABLED
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#else /* !STM32_LSI_ENABLED */
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#if STM32_RTCSEL == STM32_RTCSEL_LSI
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#error "LSI not enabled, required by STM32_RTCSEL"
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#endif
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#endif /* !STM32_LSI_ENABLED */
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/*
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* LSE related checks.
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*/
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#if STM32_LSE_ENABLED
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#if (STM32_LSECLK == 0)
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#error "LSE frequency not defined"
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#endif
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#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
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#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
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#endif
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#else /* !STM32_LSE_ENABLED */
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#if STM32_RTCSEL == STM32_RTCSEL_LSE
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#error "LSE not enabled, required by STM32_RTCSEL"
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#endif
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#endif /* !STM32_LSE_ENABLED */
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/* PLL activation conditions.*/
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#if (STM32_SW == STM32_SW_PLL) || \
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(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
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defined(__DOXYGEN__)
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/**
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* @brief PLL activation flag.
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*/
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#define STM32_ACTIVATE_PLL TRUE
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#else
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#define STM32_ACTIVATE_PLL FALSE
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#endif
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/* HSE prescaler setting check.*/
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#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
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(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
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#error "invalid STM32_PLLXTPRE value specified"
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#endif
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/**
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* @brief PLLMUL field.
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*/
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#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#else
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#error "invalid STM32_PLLMUL_VALUE value specified"
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
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#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#else
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#define STM32_PLLCLKIN (STM32_HSECLK / 2)
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#endif
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/* PLL input frequency range check.*/
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#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
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#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
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#endif
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/**
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* @brief PLL output clock frequency.
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*/
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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/* PLL output frequency range check.*/
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#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
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#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
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#endif
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/**
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* @brief System clock source.
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*/
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#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#elif (STM32_SW == STM32_SW_HSI)
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#define STM32_SYSCLK STM32_HSICLK
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#elif (STM32_SW == STM32_SW_HSE)
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#define STM32_SYSCLK STM32_HSECLK
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#else
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#error "invalid STM32_SW value specified"
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#endif
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/* Check on the system clock.*/
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#if STM32_SYSCLK > STM32_SYSCLK_MAX
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#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
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#endif
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/**
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* @brief AHB frequency.
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*/
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#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#elif STM32_HPRE == STM32_HPRE_DIV2
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#define STM32_HCLK (STM32_SYSCLK / 2)
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#elif STM32_HPRE == STM32_HPRE_DIV4
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#define STM32_HCLK (STM32_SYSCLK / 4)
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#elif STM32_HPRE == STM32_HPRE_DIV8
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#define STM32_HCLK (STM32_SYSCLK / 8)
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#elif STM32_HPRE == STM32_HPRE_DIV16
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#define STM32_HCLK (STM32_SYSCLK / 16)
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#elif STM32_HPRE == STM32_HPRE_DIV64
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#define STM32_HCLK (STM32_SYSCLK / 64)
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#elif STM32_HPRE == STM32_HPRE_DIV128
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#define STM32_HCLK (STM32_SYSCLK / 128)
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#elif STM32_HPRE == STM32_HPRE_DIV256
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#define STM32_HCLK (STM32_SYSCLK / 256)
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#elif STM32_HPRE == STM32_HPRE_DIV512
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#define STM32_HCLK (STM32_SYSCLK / 512)
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#else
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#error "invalid STM32_HPRE value specified"
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#endif
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/* AHB frequency check.*/
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#if STM32_HCLK > STM32_SYSCLK_MAX
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#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
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#endif
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/**
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* @brief APB1 frequency.
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*/
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#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
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#define STM32_PCLK1 (STM32_HCLK / 1)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV2
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#define STM32_PCLK1 (STM32_HCLK / 2)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV4
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#define STM32_PCLK1 (STM32_HCLK / 4)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV8
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#define STM32_PCLK1 (STM32_HCLK / 8)
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#elif STM32_PPRE1 == STM32_PPRE1_DIV16
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#define STM32_PCLK1 (STM32_HCLK / 16)
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#else
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#error "invalid STM32_PPRE1 value specified"
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#endif
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/* APB1 frequency check.*/
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#if STM32_PCLK1 > STM32_PCLK1_MAX
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#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
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#endif
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|
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/**
|
|
* @brief APB2 frequency.
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|
*/
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|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
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#define STM32_PCLK2 (STM32_HCLK / 1)
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#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
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#define STM32_PCLK2 (STM32_HCLK / 2)
|
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#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
|
#define STM32_PCLK2 (STM32_HCLK / 4)
|
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#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
|
#define STM32_PCLK2 (STM32_HCLK / 8)
|
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#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
|
#define STM32_PCLK2 (STM32_HCLK / 16)
|
|
#else
|
|
#error "invalid STM32_PPRE2 value specified"
|
|
#endif
|
|
|
|
/* APB2 frequency check.*/
|
|
#if STM32_PCLK2 > STM32_PCLK2_MAX
|
|
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief RTC clock.
|
|
*/
|
|
#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
|
|
#define STM32_RTCCLK STM32_LSECLK
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
|
#define STM32_RTCCLK STM32_LSICLK
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
|
#define STM32_RTCCLK (STM32_HSECLK / 128)
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
|
|
#define STM32_RTCCLK 0
|
|
#else
|
|
#error "invalid source selected for RTC clock"
|
|
#endif
|
|
|
|
/**
|
|
* @brief ADC frequency.
|
|
*/
|
|
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 2)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 4)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 6)
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 8)
|
|
#else
|
|
#error "invalid STM32_ADCPRE value specified"
|
|
#endif
|
|
|
|
/* ADC frequency check.*/
|
|
#if STM32_ADCCLK > STM32_ADCCLK_MAX
|
|
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
|
#endif
|
|
|
|
/**
|
|
* @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
|
|
*/
|
|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
|
#else
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Timers 1, 8, 9, 10, 11 clock.
|
|
*/
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
|
#else
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
|
|
#endif
|
|
|
|
/**
|
|
* @brief Flash settings.
|
|
*/
|
|
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
|
|
#define STM32_FLASHBITS 0x00000010
|
|
#elif STM32_HCLK <= 48000000
|
|
#define STM32_FLASHBITS 0x00000011
|
|
#else
|
|
#define STM32_FLASHBITS 0x00000012
|
|
#endif
|
|
|
|
#endif /* _HAL_LLD_F100_H_ */
|
|
|
|
/** @} */
|