5287 lines
411 KiB
C
5287 lines
411 KiB
C
/**
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******************************************************************************
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* @file stm32f048xx.h
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* @author MCD Application Team
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* @version V2.2.2
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* @date 26-June-2015
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* @brief CMSIS STM32F048xx devices Peripheral Access Layer Header File.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral’s registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS_Device
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* @{
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*/
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/** @addtogroup stm32f048xx
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* @{
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*/
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#ifndef __STM32F048xx_H
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#define __STM32F048xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Configuration_section_for_CMSIS
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* @{
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*/
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/**
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* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
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*/
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#define __CM0_REV 0 /*!< Core Revision r0p0 */
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#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
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#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @}
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*/
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/** @addtogroup Peripheral_interrupt_number_definition
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* @{
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*/
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/**
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* @brief STM32F048xx device Interrupt Number Definition
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*/
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typedef enum
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{
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/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
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SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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/****** STM32F048xx specific Interrupt Numbers **************************************************************/
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WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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VDDIO2_IRQn = 1, /*!< VDDIO2 Interrupt through EXTI Line 31 */
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RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
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FLASH_IRQn = 3, /*!< FLASH global Interrupt */
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RCC_CRS_IRQn = 4, /*!< RCC & CRS Global Interrupts */
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EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
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EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
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EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
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TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
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DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
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DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
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DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
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ADC1_IRQn = 12, /*!< ADC1 Interrupt */
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TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
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TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
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TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
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TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
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TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
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I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
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SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
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SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
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USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
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USART2_IRQn = 28, /*!< USART2 global Interrupt */
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CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
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USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
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} IRQn_Type;
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/**
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* @}
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*/
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#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#include "system_stm32f0xx.h" /* STM32F0xx System Header */
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#include <stdint.h>
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/** @addtogroup Peripheral_registers_structures
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* @{
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*/
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/**
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* @brief Analog to Digital Converter
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*/
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typedef struct
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{
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__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
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__IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
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__IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
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__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
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__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
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__IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
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uint32_t RESERVED1; /*!< Reserved, 0x18 */
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uint32_t RESERVED2; /*!< Reserved, 0x1C */
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__IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
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uint32_t RESERVED3; /*!< Reserved, 0x24 */
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__IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
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uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
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__IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
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}ADC_TypeDef;
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typedef struct
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{
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__IO uint32_t CCR;
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}ADC_Common_TypeDef;
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/**
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* @brief Controller Area Network TxMailBox
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*/
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typedef struct
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{
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__IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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__IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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__IO uint32_t TDLR; /*!< CAN mailbox data low register */
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__IO uint32_t TDHR; /*!< CAN mailbox data high register */
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}CAN_TxMailBox_TypeDef;
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/**
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* @brief Controller Area Network FIFOMailBox
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*/
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typedef struct
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{
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__IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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__IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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__IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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__IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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}CAN_FIFOMailBox_TypeDef;
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/**
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* @brief Controller Area Network FilterRegister
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*/
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typedef struct
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{
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__IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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__IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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}CAN_FilterRegister_TypeDef;
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/**
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* @brief Controller Area Network
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*/
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typedef struct
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{
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__IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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__IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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__IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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__IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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__IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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__IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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__IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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__IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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__IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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__IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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uint32_t RESERVED2; /*!< Reserved, 0x208 */
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__IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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uint32_t RESERVED3; /*!< Reserved, 0x210 */
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__IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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uint32_t RESERVED4; /*!< Reserved, 0x218 */
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__IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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}CAN_TypeDef;
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/**
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* @brief HDMI-CEC
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
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__IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
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__IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
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__IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
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__IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
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__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
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}CEC_TypeDef;
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/**
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* @brief CRC calculation unit
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*/
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typedef struct
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{
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__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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uint8_t RESERVED0; /*!< Reserved, 0x05 */
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uint16_t RESERVED1; /*!< Reserved, 0x06 */
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__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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uint32_t RESERVED2; /*!< Reserved, 0x0C */
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__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
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__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
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}CRC_TypeDef;
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/**
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* @brief Clock Recovery System
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*/
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typedef struct
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{
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__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
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__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
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__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
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__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
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}CRS_TypeDef;
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/**
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* @brief Debug MCU
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*/
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typedef struct
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{
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__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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}DBGMCU_TypeDef;
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/**
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* @brief DMA Controller
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*/
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typedef struct
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{
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__IO uint32_t CCR; /*!< DMA channel x configuration register */
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__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
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__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
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__IO uint32_t CMAR; /*!< DMA channel x memory address register */
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}DMA_Channel_TypeDef;
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typedef struct
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{
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__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
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__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
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}DMA_TypeDef;
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/**
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* @brief External Interrupt/Event Controller
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*/
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typedef struct
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{
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__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
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__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
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__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
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__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
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__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
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__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
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}EXTI_TypeDef;
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/**
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* @brief FLASH Registers
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*/
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typedef struct
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{
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__IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
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__IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
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__IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
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__IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
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__IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
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__IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
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__IO uint32_t RESERVED; /*!< Reserved, 0x18 */
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__IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
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__IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
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}FLASH_TypeDef;
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/**
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* @brief Option Bytes Registers
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*/
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typedef struct
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{
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__IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
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__IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
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__IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
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__IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
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__IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
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__IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
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}OB_TypeDef;
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/**
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* @brief General Purpose I/O
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*/
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typedef struct
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{
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__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
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__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
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__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
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__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
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}GPIO_TypeDef;
|
||
|
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/**
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* @brief SysTem Configuration
|
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*/
|
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typedef struct
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{
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__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
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uint32_t RESERVED; /*!< Reserved, 0x04 */
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__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
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__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
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}SYSCFG_TypeDef;
|
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|
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/**
|
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* @brief Inter-integrated Circuit Interface
|
||
*/
|
||
|
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typedef struct
|
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{
|
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__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
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__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
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__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
|
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__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
|
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__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
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__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
|
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__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
|
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__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
|
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__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
|
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__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
|
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__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
|
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}I2C_TypeDef;
|
||
|
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/**
|
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* @brief Independent WATCHDOG
|
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*/
|
||
|
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typedef struct
|
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{
|
||
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
|
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__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
|
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__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
|
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__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
|
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__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
|
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}IWDG_TypeDef;
|
||
|
||
/**
|
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* @brief Power Control
|
||
*/
|
||
|
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typedef struct
|
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{
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__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
|
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__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
|
||
}PWR_TypeDef;
|
||
|
||
/**
|
||
* @brief Reset and Clock Control
|
||
*/
|
||
|
||
typedef struct
|
||
{
|
||
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
||
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
|
||
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
|
||
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
|
||
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
|
||
__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
|
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__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
|
||
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
|
||
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
|
||
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
|
||
__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
|
||
__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
|
||
__IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
|
||
__IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
|
||
}RCC_TypeDef;
|
||
|
||
/**
|
||
* @brief Real-Time Clock
|
||
*/
|
||
typedef struct
|
||
{
|
||
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
||
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
||
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
||
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
||
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
||
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
|
||
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
|
||
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
||
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
|
||
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
||
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
||
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
||
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
||
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
||
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
||
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
|
||
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
|
||
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
|
||
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
|
||
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
|
||
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
|
||
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
||
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
||
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
||
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
||
}RTC_TypeDef;
|
||
|
||
/**
|
||
* @brief Serial Peripheral Interface
|
||
*/
|
||
|
||
typedef struct
|
||
{
|
||
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
||
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
||
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
||
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
||
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
||
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
||
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
||
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
||
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
||
}SPI_TypeDef;
|
||
|
||
/**
|
||
* @brief TIM
|
||
*/
|
||
typedef struct
|
||
{
|
||
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
||
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
||
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
|
||
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
||
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
||
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
||
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
||
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
||
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
||
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
||
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
|
||
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
||
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
||
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
||
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
||
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
||
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
||
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
||
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
||
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
|
||
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
|
||
}TIM_TypeDef;
|
||
|
||
/**
|
||
* @brief Touch Sensing Controller (TSC)
|
||
*/
|
||
typedef struct
|
||
{
|
||
__IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
|
||
__IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
|
||
__IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
|
||
__IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
|
||
__IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
|
||
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
|
||
__IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
|
||
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
|
||
__IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
|
||
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
|
||
__IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
|
||
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
|
||
__IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
|
||
__IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
|
||
}TSC_TypeDef;
|
||
|
||
/**
|
||
* @brief Universal Synchronous Asynchronous Receiver Transmitter
|
||
*/
|
||
|
||
typedef struct
|
||
{
|
||
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
|
||
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
|
||
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
|
||
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
|
||
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
|
||
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
|
||
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
|
||
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
|
||
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
|
||
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
|
||
uint16_t RESERVED1; /*!< Reserved, 0x26 */
|
||
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
|
||
uint16_t RESERVED2; /*!< Reserved, 0x2A */
|
||
}USART_TypeDef;
|
||
|
||
/**
|
||
* @brief Universal Serial Bus Full Speed Device
|
||
*/
|
||
|
||
typedef struct
|
||
{
|
||
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
|
||
__IO uint16_t RESERVED0; /*!< Reserved */
|
||
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
|
||
__IO uint16_t RESERVED1; /*!< Reserved */
|
||
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
|
||
__IO uint16_t RESERVED2; /*!< Reserved */
|
||
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
|
||
__IO uint16_t RESERVED3; /*!< Reserved */
|
||
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
|
||
__IO uint16_t RESERVED4; /*!< Reserved */
|
||
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
|
||
__IO uint16_t RESERVED5; /*!< Reserved */
|
||
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
|
||
__IO uint16_t RESERVED6; /*!< Reserved */
|
||
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
|
||
__IO uint16_t RESERVED7[17]; /*!< Reserved */
|
||
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
|
||
__IO uint16_t RESERVED8; /*!< Reserved */
|
||
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
|
||
__IO uint16_t RESERVED9; /*!< Reserved */
|
||
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
|
||
__IO uint16_t RESERVEDA; /*!< Reserved */
|
||
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
|
||
__IO uint16_t RESERVEDB; /*!< Reserved */
|
||
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
|
||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
|
||
__IO uint16_t RESERVEDD; /*!< Reserved */
|
||
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
|
||
__IO uint16_t RESERVEDE; /*!< Reserved */
|
||
}USB_TypeDef;
|
||
|
||
/**
|
||
* @brief Window WATCHDOG
|
||
*/
|
||
typedef struct
|
||
{
|
||
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
||
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
||
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
||
}WWDG_TypeDef;
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/** @addtogroup Peripheral_memory_map
|
||
* @{
|
||
*/
|
||
|
||
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
|
||
#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
|
||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
|
||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||
|
||
/*!< Peripheral memory map */
|
||
#define APBPERIPH_BASE PERIPH_BASE
|
||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
|
||
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
|
||
|
||
#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
|
||
#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
|
||
#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
|
||
#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
|
||
#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
|
||
#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
|
||
#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
|
||
#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
|
||
#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
|
||
#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
|
||
#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
|
||
#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
|
||
#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
|
||
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
|
||
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
|
||
|
||
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
|
||
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
|
||
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
|
||
#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
|
||
#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
|
||
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
|
||
#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
|
||
#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
|
||
#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
|
||
#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
|
||
|
||
#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
|
||
#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
|
||
#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
|
||
#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
|
||
#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
|
||
#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
|
||
#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
|
||
#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
|
||
|
||
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
|
||
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
|
||
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
|
||
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
|
||
#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
|
||
|
||
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
|
||
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
|
||
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
|
||
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/** @addtogroup Peripheral_declaration
|
||
* @{
|
||
*/
|
||
|
||
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
||
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
||
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
|
||
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
||
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
||
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
||
#define USART2 ((USART_TypeDef *) USART2_BASE)
|
||
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
||
#define CAN ((CAN_TypeDef *) CAN_BASE)
|
||
#define CRS ((CRS_TypeDef *) CRS_BASE)
|
||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||
#define CEC ((CEC_TypeDef *) CEC_BASE)
|
||
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
|
||
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
||
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
||
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
||
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
||
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
||
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
|
||
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
||
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
||
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
|
||
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
|
||
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
||
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
||
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
||
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
||
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
||
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
||
#define OB ((OB_TypeDef *) OB_BASE)
|
||
#define RCC ((RCC_TypeDef *) RCC_BASE)
|
||
#define CRC ((CRC_TypeDef *) CRC_BASE)
|
||
#define TSC ((TSC_TypeDef *) TSC_BASE)
|
||
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
||
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
||
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
||
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
|
||
#define USB ((USB_TypeDef *) USB_BASE)
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/** @addtogroup Exported_constants
|
||
* @{
|
||
*/
|
||
|
||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||
* @{
|
||
*/
|
||
|
||
/******************************************************************************/
|
||
/* Peripheral Registers Bits Definition */
|
||
/******************************************************************************/
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Analog to Digital Converter (ADC) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************** Bits definition for ADC_ISR register ******************/
|
||
#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
|
||
#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
|
||
#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
|
||
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
|
||
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
|
||
#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
|
||
|
||
/* Old EOSEQ bit definition, maintained for legacy purpose */
|
||
#define ADC_ISR_EOS ADC_ISR_EOSEQ
|
||
|
||
/******************** Bits definition for ADC_IER register ******************/
|
||
#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
|
||
#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
|
||
#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
|
||
#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
|
||
#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
|
||
#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
|
||
|
||
/* Old EOSEQIE bit definition, maintained for legacy purpose */
|
||
#define ADC_IER_EOSIE ADC_IER_EOSEQIE
|
||
|
||
/******************** Bits definition for ADC_CR register *******************/
|
||
#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
|
||
#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
|
||
#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
|
||
#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
|
||
#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
|
||
|
||
/******************* Bits definition for ADC_CFGR1 register *****************/
|
||
#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
|
||
#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
|
||
#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
|
||
#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
|
||
#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
|
||
#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
|
||
#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
|
||
#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
|
||
#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
|
||
#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
|
||
#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
|
||
#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
|
||
#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
|
||
#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
|
||
#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
||
#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
||
#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
|
||
#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
|
||
#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
|
||
#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
|
||
#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
|
||
#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
|
||
#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
||
#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
||
#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
|
||
#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
|
||
#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
|
||
|
||
/* Old WAIT bit definition, maintained for legacy purpose */
|
||
#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
|
||
|
||
/******************* Bits definition for ADC_CFGR2 register *****************/
|
||
#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
|
||
#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
|
||
#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
|
||
|
||
/* Old bit definition, maintained for legacy purpose */
|
||
#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
|
||
#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
|
||
|
||
/****************** Bit definition for ADC_SMPR register ********************/
|
||
#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
|
||
#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||
#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||
#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||
|
||
/* Old bit definition, maintained for legacy purpose */
|
||
#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
|
||
#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
|
||
#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
|
||
#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
|
||
|
||
/******************* Bit definition for ADC_TR register ********************/
|
||
#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
|
||
#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
|
||
|
||
/* Old bit definition, maintained for legacy purpose */
|
||
#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
|
||
#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
|
||
|
||
/****************** Bit definition for ADC_CHSELR register ******************/
|
||
#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
|
||
#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
|
||
#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
|
||
#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
|
||
#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
|
||
#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
|
||
#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
|
||
#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
|
||
#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
|
||
#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
|
||
#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
|
||
#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
|
||
#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
|
||
#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
|
||
#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
|
||
#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
|
||
#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
|
||
#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
|
||
#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
|
||
|
||
/******************** Bit definition for ADC_DR register ********************/
|
||
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
|
||
|
||
/******************* Bit definition for ADC_CCR register ********************/
|
||
#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
|
||
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
|
||
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Controller Area Network (CAN ) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/*!<CAN control and status registers */
|
||
/******************* Bit definition for CAN_MCR register ********************/
|
||
#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
|
||
#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
|
||
#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
|
||
#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
|
||
#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
|
||
#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
|
||
#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
|
||
#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
|
||
#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
|
||
|
||
/******************* Bit definition for CAN_MSR register ********************/
|
||
#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
|
||
#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
|
||
#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
|
||
#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
|
||
#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
|
||
#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
|
||
#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
|
||
#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
|
||
#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
|
||
|
||
/******************* Bit definition for CAN_TSR register ********************/
|
||
#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
|
||
#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
|
||
#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
|
||
#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
|
||
#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
|
||
#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
|
||
#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
|
||
#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
|
||
#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
|
||
#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
|
||
#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
|
||
#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
|
||
#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
|
||
#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
|
||
#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
|
||
#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
|
||
|
||
#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
|
||
#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
|
||
#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
|
||
#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
|
||
|
||
#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
|
||
#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
|
||
#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
|
||
#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
|
||
|
||
/******************* Bit definition for CAN_RF0R register *******************/
|
||
#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
|
||
#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
|
||
#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
|
||
#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
|
||
|
||
/******************* Bit definition for CAN_RF1R register *******************/
|
||
#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
|
||
#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
|
||
#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
|
||
#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
|
||
|
||
/******************** Bit definition for CAN_IER register *******************/
|
||
#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
|
||
#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
|
||
#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
|
||
#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
|
||
#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
|
||
#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
|
||
#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
|
||
#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
|
||
#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
|
||
#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
|
||
#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
|
||
#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
|
||
#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
|
||
#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
|
||
|
||
/******************** Bit definition for CAN_ESR register *******************/
|
||
#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
|
||
#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
|
||
#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
|
||
|
||
#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
|
||
#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
|
||
#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
||
#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
|
||
|
||
/******************* Bit definition for CAN_BTR register ********************/
|
||
#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
|
||
#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
|
||
#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
|
||
#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
|
||
#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
|
||
#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
|
||
#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
|
||
#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
|
||
#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
|
||
#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
|
||
#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
|
||
#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
|
||
#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
|
||
#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
|
||
#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
|
||
|
||
/*!<Mailbox registers */
|
||
/****************** Bit definition for CAN_TI0R register ********************/
|
||
#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
||
#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
||
#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
||
#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
||
#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
||
|
||
/****************** Bit definition for CAN_TDT0R register *******************/
|
||
#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
||
#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
||
#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
||
|
||
/****************** Bit definition for CAN_TDL0R register *******************/
|
||
#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
||
#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
||
#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
||
#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
||
|
||
/****************** Bit definition for CAN_TDH0R register *******************/
|
||
#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
||
#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
||
#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
||
#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
||
|
||
/******************* Bit definition for CAN_TI1R register *******************/
|
||
#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
||
#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
||
#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
||
#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
||
#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
||
|
||
/******************* Bit definition for CAN_TDT1R register ******************/
|
||
#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
||
#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
||
#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
||
|
||
/******************* Bit definition for CAN_TDL1R register ******************/
|
||
#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
||
#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
||
#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
||
#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
||
|
||
/******************* Bit definition for CAN_TDH1R register ******************/
|
||
#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
||
#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
||
#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
||
#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
||
|
||
/******************* Bit definition for CAN_TI2R register *******************/
|
||
#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
||
#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
||
#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
||
#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
||
#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
||
|
||
/******************* Bit definition for CAN_TDT2R register ******************/
|
||
#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
||
#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
||
#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
||
|
||
/******************* Bit definition for CAN_TDL2R register ******************/
|
||
#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
||
#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
||
#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
||
#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
||
|
||
/******************* Bit definition for CAN_TDH2R register ******************/
|
||
#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
||
#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
||
#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
||
#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
||
|
||
/******************* Bit definition for CAN_RI0R register *******************/
|
||
#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
||
#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
||
#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
||
#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
||
|
||
/******************* Bit definition for CAN_RDT0R register ******************/
|
||
#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
||
#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
||
#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
||
|
||
/******************* Bit definition for CAN_RDL0R register ******************/
|
||
#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
||
#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
||
#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
||
#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
||
|
||
/******************* Bit definition for CAN_RDH0R register ******************/
|
||
#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
||
#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
||
#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
||
#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
||
|
||
/******************* Bit definition for CAN_RI1R register *******************/
|
||
#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
||
#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
||
#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
||
#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
||
|
||
/******************* Bit definition for CAN_RDT1R register ******************/
|
||
#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
||
#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
||
#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
||
|
||
/******************* Bit definition for CAN_RDL1R register ******************/
|
||
#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
||
#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
||
#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
||
#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
||
|
||
/******************* Bit definition for CAN_RDH1R register ******************/
|
||
#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
||
#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
||
#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
||
#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
||
|
||
/*!<CAN filter registers */
|
||
/******************* Bit definition for CAN_FMR register ********************/
|
||
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
|
||
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
|
||
|
||
/******************* Bit definition for CAN_FM1R register *******************/
|
||
#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
|
||
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
|
||
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
|
||
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
|
||
#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
|
||
#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
|
||
#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
|
||
#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
|
||
#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
|
||
#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
|
||
#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
|
||
#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
|
||
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
|
||
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
|
||
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
|
||
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
|
||
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
|
||
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
|
||
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
|
||
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
|
||
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
|
||
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
|
||
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
|
||
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
|
||
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
|
||
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
|
||
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
|
||
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
|
||
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
|
||
|
||
/******************* Bit definition for CAN_FS1R register *******************/
|
||
#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
|
||
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
|
||
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
|
||
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
|
||
#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
|
||
#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
|
||
#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
|
||
#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
|
||
#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
|
||
#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
|
||
#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
|
||
#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
|
||
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
|
||
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
|
||
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
|
||
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
|
||
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
|
||
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
|
||
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
|
||
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
|
||
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
|
||
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
|
||
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
|
||
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
|
||
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
|
||
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
|
||
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
|
||
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
|
||
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
|
||
|
||
/****************** Bit definition for CAN_FFA1R register *******************/
|
||
#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
|
||
#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
|
||
#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
|
||
#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
|
||
#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
|
||
#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
|
||
#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
|
||
#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
|
||
#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
|
||
#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
|
||
#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
|
||
#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
|
||
#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
|
||
#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
|
||
#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
|
||
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
|
||
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
|
||
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
|
||
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
|
||
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
|
||
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
|
||
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
|
||
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
|
||
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
|
||
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
|
||
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
|
||
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
|
||
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
|
||
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
|
||
|
||
/******************* Bit definition for CAN_FA1R register *******************/
|
||
#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
|
||
#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
|
||
#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
|
||
#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
|
||
#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
|
||
#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
|
||
#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
|
||
#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
|
||
#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
|
||
#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
|
||
#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
|
||
#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
|
||
#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
|
||
#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
|
||
#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
|
||
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
|
||
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
|
||
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
|
||
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
|
||
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
|
||
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
|
||
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
|
||
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
|
||
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
|
||
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
|
||
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
|
||
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
|
||
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
|
||
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
|
||
|
||
/******************* Bit definition for CAN_F0R1 register *******************/
|
||
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F1R1 register *******************/
|
||
#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F2R1 register *******************/
|
||
#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F3R1 register *******************/
|
||
#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F4R1 register *******************/
|
||
#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F5R1 register *******************/
|
||
#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F6R1 register *******************/
|
||
#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F7R1 register *******************/
|
||
#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F8R1 register *******************/
|
||
#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F9R1 register *******************/
|
||
#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F10R1 register ******************/
|
||
#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F11R1 register ******************/
|
||
#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F12R1 register ******************/
|
||
#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F13R1 register ******************/
|
||
#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F0R2 register *******************/
|
||
#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F1R2 register *******************/
|
||
#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F2R2 register *******************/
|
||
#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F3R2 register *******************/
|
||
#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F4R2 register *******************/
|
||
#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F5R2 register *******************/
|
||
#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F6R2 register *******************/
|
||
#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F7R2 register *******************/
|
||
#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F8R2 register *******************/
|
||
#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F9R2 register *******************/
|
||
#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F10R2 register ******************/
|
||
#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F11R2 register ******************/
|
||
#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F12R2 register ******************/
|
||
#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************* Bit definition for CAN_F13R2 register ******************/
|
||
#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
||
#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
||
#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
||
#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
||
#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
||
#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
||
#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
||
#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
||
#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
||
#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
||
#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
||
#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
||
#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
||
#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
||
#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
||
#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
||
#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
||
#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
||
#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
||
#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
||
#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
||
#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
||
#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
||
#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
||
#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
||
#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
||
#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
||
#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
||
#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
||
#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
||
#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
||
#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* HDMI-CEC (CEC) */
|
||
/* */
|
||
/******************************************************************************/
|
||
|
||
/******************* Bit definition for CEC_CR register *********************/
|
||
#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
|
||
#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
|
||
#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
|
||
|
||
/******************* Bit definition for CEC_CFGR register *******************/
|
||
#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
|
||
#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
|
||
#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
|
||
#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
|
||
#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
|
||
#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
|
||
#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
|
||
#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
|
||
#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
|
||
|
||
/******************* Bit definition for CEC_TXDR register *******************/
|
||
#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
|
||
|
||
/******************* Bit definition for CEC_RXDR register *******************/
|
||
#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
|
||
|
||
/******************* Bit definition for CEC_ISR register ********************/
|
||
#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
|
||
#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
|
||
#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
|
||
#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
|
||
#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
|
||
#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
|
||
#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
|
||
#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
|
||
#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
|
||
#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
|
||
#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
|
||
#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
|
||
#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
|
||
|
||
/******************* Bit definition for CEC_IER register ********************/
|
||
#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
|
||
#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
|
||
#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
|
||
#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
|
||
#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
|
||
#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
|
||
#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
|
||
#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
|
||
#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
|
||
#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
|
||
#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
|
||
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
|
||
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* CRC calculation unit (CRC) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************* Bit definition for CRC_DR register *********************/
|
||
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
||
|
||
/******************* Bit definition for CRC_IDR register ********************/
|
||
#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
||
|
||
/******************** Bit definition for CRC_CR register ********************/
|
||
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
|
||
#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
|
||
#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
|
||
#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
|
||
#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
|
||
|
||
/******************* Bit definition for CRC_INIT register *******************/
|
||
#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* CRS Clock Recovery System */
|
||
/******************************************************************************/
|
||
|
||
/******************* Bit definition for CRS_CR register *********************/
|
||
#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
|
||
#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
|
||
#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
|
||
#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
|
||
#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
|
||
#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
|
||
#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
|
||
#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
|
||
|
||
/******************* Bit definition for CRS_CFGR register *********************/
|
||
#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
|
||
#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
|
||
|
||
#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
|
||
#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
|
||
#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
|
||
#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
|
||
|
||
#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
|
||
#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
|
||
#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
|
||
|
||
#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
|
||
|
||
/******************* Bit definition for CRS_ISR register *********************/
|
||
#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
|
||
#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
|
||
#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
|
||
#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
|
||
#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
|
||
#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
|
||
#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
|
||
#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
|
||
#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
|
||
|
||
/******************* Bit definition for CRS_ICR register *********************/
|
||
#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
|
||
#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
|
||
#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
|
||
#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Debug MCU (DBGMCU) */
|
||
/* */
|
||
/******************************************************************************/
|
||
|
||
/**************** Bit definition for DBGMCU_IDCODE register *****************/
|
||
#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
|
||
|
||
#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
|
||
#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||
#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||
#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
|
||
#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
|
||
#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
|
||
#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
|
||
#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
|
||
#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
|
||
#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
|
||
#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
|
||
#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
|
||
#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
|
||
#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
|
||
#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
|
||
#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
|
||
#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
|
||
|
||
/****************** Bit definition for DBGMCU_CR register *******************/
|
||
#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
|
||
#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
|
||
|
||
/****************** Bit definition for DBGMCU_APB1_FZ register **************/
|
||
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
|
||
#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
|
||
|
||
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
|
||
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
|
||
#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
|
||
#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* DMA Controller (DMA) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************* Bit definition for DMA_ISR register ********************/
|
||
#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
|
||
#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
|
||
#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
|
||
#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
|
||
#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
|
||
#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
|
||
#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
|
||
#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
|
||
#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
|
||
#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
|
||
#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
|
||
#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
|
||
#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
|
||
#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
|
||
#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
|
||
#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
|
||
#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
|
||
#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
|
||
#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
|
||
#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
|
||
#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
|
||
#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
|
||
|
||
/******************* Bit definition for DMA_IFCR register *******************/
|
||
#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
|
||
#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
|
||
#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
|
||
#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
|
||
#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
|
||
#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
|
||
#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
|
||
#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
|
||
#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
|
||
#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
|
||
|
||
/******************* Bit definition for DMA_CCR register ********************/
|
||
#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
|
||
#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
|
||
#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
|
||
#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
|
||
#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
|
||
#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
|
||
#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
|
||
#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
|
||
|
||
#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
|
||
#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
||
#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
||
|
||
#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
|
||
#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
||
#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
||
|
||
#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
|
||
#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
||
#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
||
|
||
#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
|
||
|
||
/****************** Bit definition for DMA_CNDTR register *******************/
|
||
#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
|
||
|
||
/****************** Bit definition for DMA_CPAR register ********************/
|
||
#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
|
||
|
||
/****************** Bit definition for DMA_CMAR register ********************/
|
||
#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* External Interrupt/Event Controller (EXTI) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************* Bit definition for EXTI_IMR register *******************/
|
||
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
||
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
||
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
||
#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
|
||
#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
|
||
#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
|
||
#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
|
||
#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
|
||
#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
|
||
#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
|
||
#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
|
||
#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
|
||
#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
|
||
#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
|
||
#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
|
||
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
|
||
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
||
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
||
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
|
||
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
|
||
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
|
||
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
|
||
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
|
||
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
|
||
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
|
||
|
||
/****************** Bit definition for EXTI_EMR register ********************/
|
||
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
||
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
||
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
||
#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
|
||
#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
|
||
#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
|
||
#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
|
||
#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
|
||
#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
|
||
#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
|
||
#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
|
||
#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
|
||
#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
|
||
#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
|
||
#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
|
||
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
|
||
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
||
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
||
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
|
||
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
|
||
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
|
||
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
|
||
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
|
||
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
|
||
|
||
/******************* Bit definition for EXTI_RTSR register ******************/
|
||
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
||
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
||
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
||
#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
|
||
#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
|
||
#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
|
||
#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
|
||
#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
|
||
#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
|
||
#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
|
||
#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
|
||
#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
|
||
#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
|
||
#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
|
||
#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
|
||
#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
||
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
||
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
||
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
||
|
||
/******************* Bit definition for EXTI_FTSR register *******************/
|
||
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
||
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
||
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
||
#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
|
||
#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
|
||
#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
|
||
#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
|
||
#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
|
||
#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
|
||
#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
|
||
#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
|
||
#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
|
||
#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
|
||
#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
|
||
#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
|
||
#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
||
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
||
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
||
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
||
|
||
/******************* Bit definition for EXTI_SWIER register *******************/
|
||
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
||
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
||
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
||
#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
|
||
#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
|
||
#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
|
||
#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
|
||
#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
|
||
#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
|
||
#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
|
||
#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
|
||
#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
|
||
#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
|
||
#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
|
||
#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
|
||
#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
||
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
||
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
||
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
||
|
||
/****************** Bit definition for EXTI_PR register *********************/
|
||
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
|
||
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
|
||
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
|
||
#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
|
||
#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
|
||
#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
|
||
#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
|
||
#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
|
||
#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
|
||
#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
|
||
#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
|
||
#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
|
||
#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
|
||
#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
|
||
#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
|
||
#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
|
||
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
|
||
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
|
||
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* FLASH and Option Bytes Registers */
|
||
/* */
|
||
/******************************************************************************/
|
||
|
||
/******************* Bit definition for FLASH_ACR register ******************/
|
||
#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
|
||
|
||
#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
|
||
#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
|
||
|
||
/****************** Bit definition for FLASH_KEYR register ******************/
|
||
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
|
||
|
||
/***************** Bit definition for FLASH_OPTKEYR register ****************/
|
||
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
|
||
|
||
/****************** FLASH Keys **********************************************/
|
||
#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
|
||
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
|
||
to unlock the write access to the FPEC. */
|
||
|
||
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
|
||
#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
|
||
unlock the write access to the option byte block */
|
||
|
||
/****************** Bit definition for FLASH_SR register *******************/
|
||
#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
|
||
#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
|
||
#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
|
||
#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
|
||
#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
|
||
|
||
/******************* Bit definition for FLASH_CR register *******************/
|
||
#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
|
||
#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
|
||
#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
|
||
#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
|
||
#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
|
||
#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
|
||
#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
|
||
#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
|
||
#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
|
||
#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
|
||
#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
|
||
|
||
/******************* Bit definition for FLASH_AR register *******************/
|
||
#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
|
||
|
||
/****************** Bit definition for FLASH_OBR register *******************/
|
||
#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
|
||
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
|
||
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
|
||
|
||
#define FLASH_OBR_USER ((uint32_t)0x0000FF00) /*!< User Option Bytes */
|
||
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
|
||
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
|
||
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
|
||
#define FLASH_OBR_nBOOT0 ((uint32_t)0x00001000) /*!< nBOOT0 */
|
||
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
|
||
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
|
||
#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
|
||
#define FLASH_OBR_BOOT_SEL ((uint32_t)0x00008000) /*!< BOOT selection */
|
||
|
||
/* Old BOOT1 bit definition, maintained for legacy purpose */
|
||
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
|
||
|
||
/* Old OBR_VDDA bit definition, maintained for legacy purpose */
|
||
#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
|
||
|
||
/****************** Bit definition for FLASH_WRPR register ******************/
|
||
#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
|
||
|
||
/*----------------------------------------------------------------------------*/
|
||
|
||
/****************** Bit definition for OB_RDP register **********************/
|
||
#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
|
||
#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
|
||
|
||
/****************** Bit definition for OB_USER register *********************/
|
||
#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
|
||
#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
|
||
|
||
/****************** Bit definition for OB_WRP0 register *********************/
|
||
#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
|
||
#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* General Purpose IOs (GPIO) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************* Bit definition for GPIO_MODER register *****************/
|
||
#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
|
||
#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
|
||
#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
|
||
#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
|
||
#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
|
||
#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
|
||
#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
|
||
#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
|
||
#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
|
||
#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
|
||
#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
|
||
#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
|
||
#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
|
||
#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
|
||
#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
|
||
#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
|
||
#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
|
||
#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
|
||
#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
|
||
#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
|
||
#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
|
||
#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
|
||
#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
|
||
#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
|
||
#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
|
||
#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
|
||
#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
|
||
#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
|
||
#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
|
||
#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
|
||
#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
|
||
#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
|
||
#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
|
||
#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
|
||
#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
|
||
#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
|
||
#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
|
||
#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
|
||
#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
|
||
#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
|
||
#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
|
||
#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
|
||
#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
|
||
#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
|
||
#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
|
||
#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
|
||
#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
|
||
#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
|
||
|
||
/****************** Bit definition for GPIO_OTYPER register *****************/
|
||
#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
|
||
#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
|
||
#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
|
||
#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
|
||
#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
|
||
#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
|
||
#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
|
||
#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
|
||
#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
|
||
#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
|
||
#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
|
||
#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
|
||
#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
|
||
#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
|
||
#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
|
||
#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
|
||
|
||
/**************** Bit definition for GPIO_OSPEEDR register ******************/
|
||
#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
|
||
#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
|
||
#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
|
||
#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
|
||
#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
|
||
#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
|
||
#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
|
||
#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
|
||
#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
|
||
#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
|
||
#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
|
||
#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
|
||
#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
|
||
#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
|
||
#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
|
||
#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
|
||
#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
|
||
#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
|
||
#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
|
||
#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
|
||
#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
|
||
#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
|
||
#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
|
||
#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
|
||
#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
|
||
#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
|
||
#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
|
||
#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
|
||
#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
|
||
#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
|
||
#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
|
||
#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
|
||
#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
|
||
#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
|
||
#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
|
||
#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
|
||
#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
|
||
#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
|
||
|
||
/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
|
||
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
|
||
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
|
||
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
|
||
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
|
||
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
|
||
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
|
||
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
|
||
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
|
||
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
|
||
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
|
||
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
|
||
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
|
||
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
|
||
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
|
||
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
|
||
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
|
||
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
|
||
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
|
||
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
|
||
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
|
||
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
|
||
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
|
||
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
|
||
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
|
||
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
|
||
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
|
||
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
|
||
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
|
||
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
|
||
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
|
||
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
|
||
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
|
||
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
|
||
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
|
||
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
|
||
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
|
||
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
|
||
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
|
||
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
|
||
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
|
||
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
|
||
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
|
||
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
|
||
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
|
||
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
|
||
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
|
||
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
|
||
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
|
||
|
||
/******************* Bit definition for GPIO_PUPDR register ******************/
|
||
#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
|
||
#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
|
||
#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
|
||
#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
|
||
#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
|
||
#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
|
||
#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
|
||
#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
|
||
#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
|
||
#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
|
||
#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
|
||
#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
|
||
#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
|
||
#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
|
||
#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
|
||
#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
|
||
#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
|
||
#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
|
||
#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
|
||
#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
|
||
#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
|
||
#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
|
||
#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
|
||
#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
|
||
#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
|
||
#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
|
||
#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
|
||
#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
|
||
#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
|
||
#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
|
||
#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
|
||
#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
|
||
#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
|
||
#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
|
||
#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
|
||
#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
|
||
#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
|
||
#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
|
||
#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
|
||
#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
|
||
#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
|
||
#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
|
||
#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
|
||
#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
|
||
#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
|
||
#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
|
||
#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
|
||
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
|
||
|
||
/******************* Bit definition for GPIO_IDR register *******************/
|
||
#define GPIO_IDR_0 ((uint32_t)0x00000001)
|
||
#define GPIO_IDR_1 ((uint32_t)0x00000002)
|
||
#define GPIO_IDR_2 ((uint32_t)0x00000004)
|
||
#define GPIO_IDR_3 ((uint32_t)0x00000008)
|
||
#define GPIO_IDR_4 ((uint32_t)0x00000010)
|
||
#define GPIO_IDR_5 ((uint32_t)0x00000020)
|
||
#define GPIO_IDR_6 ((uint32_t)0x00000040)
|
||
#define GPIO_IDR_7 ((uint32_t)0x00000080)
|
||
#define GPIO_IDR_8 ((uint32_t)0x00000100)
|
||
#define GPIO_IDR_9 ((uint32_t)0x00000200)
|
||
#define GPIO_IDR_10 ((uint32_t)0x00000400)
|
||
#define GPIO_IDR_11 ((uint32_t)0x00000800)
|
||
#define GPIO_IDR_12 ((uint32_t)0x00001000)
|
||
#define GPIO_IDR_13 ((uint32_t)0x00002000)
|
||
#define GPIO_IDR_14 ((uint32_t)0x00004000)
|
||
#define GPIO_IDR_15 ((uint32_t)0x00008000)
|
||
|
||
/****************** Bit definition for GPIO_ODR register ********************/
|
||
#define GPIO_ODR_0 ((uint32_t)0x00000001)
|
||
#define GPIO_ODR_1 ((uint32_t)0x00000002)
|
||
#define GPIO_ODR_2 ((uint32_t)0x00000004)
|
||
#define GPIO_ODR_3 ((uint32_t)0x00000008)
|
||
#define GPIO_ODR_4 ((uint32_t)0x00000010)
|
||
#define GPIO_ODR_5 ((uint32_t)0x00000020)
|
||
#define GPIO_ODR_6 ((uint32_t)0x00000040)
|
||
#define GPIO_ODR_7 ((uint32_t)0x00000080)
|
||
#define GPIO_ODR_8 ((uint32_t)0x00000100)
|
||
#define GPIO_ODR_9 ((uint32_t)0x00000200)
|
||
#define GPIO_ODR_10 ((uint32_t)0x00000400)
|
||
#define GPIO_ODR_11 ((uint32_t)0x00000800)
|
||
#define GPIO_ODR_12 ((uint32_t)0x00001000)
|
||
#define GPIO_ODR_13 ((uint32_t)0x00002000)
|
||
#define GPIO_ODR_14 ((uint32_t)0x00004000)
|
||
#define GPIO_ODR_15 ((uint32_t)0x00008000)
|
||
|
||
/****************** Bit definition for GPIO_BSRR register ********************/
|
||
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
|
||
#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
|
||
#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
|
||
#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
|
||
#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
|
||
#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
|
||
#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
|
||
#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
|
||
#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
|
||
#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
|
||
#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
|
||
#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
|
||
#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
|
||
#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
|
||
#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
|
||
#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
|
||
#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
|
||
#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
|
||
#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
|
||
#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
|
||
#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
|
||
#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
|
||
#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
|
||
#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
|
||
#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
|
||
#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
|
||
#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
|
||
#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
|
||
#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
|
||
#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
|
||
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
|
||
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
|
||
|
||
/****************** Bit definition for GPIO_LCKR register ********************/
|
||
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
|
||
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
|
||
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
|
||
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
|
||
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
|
||
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
|
||
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
|
||
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
|
||
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
|
||
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
|
||
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
|
||
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
|
||
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
|
||
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
|
||
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
|
||
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
|
||
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
|
||
|
||
/****************** Bit definition for GPIO_AFRL register ********************/
|
||
#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
|
||
#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
|
||
#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
|
||
#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
|
||
#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
|
||
#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
|
||
#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
|
||
#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
|
||
|
||
/****************** Bit definition for GPIO_AFRH register ********************/
|
||
#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
|
||
#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
|
||
#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
|
||
#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
|
||
#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
|
||
#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
|
||
#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
|
||
#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
|
||
|
||
/****************** Bit definition for GPIO_BRR register *********************/
|
||
#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
|
||
#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
|
||
#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
|
||
#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
|
||
#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
|
||
#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
|
||
#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
|
||
#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
|
||
#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
|
||
#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
|
||
#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
|
||
#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
|
||
#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
|
||
#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
|
||
#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
|
||
#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Inter-integrated Circuit Interface (I2C) */
|
||
/* */
|
||
/******************************************************************************/
|
||
|
||
/******************* Bit definition for I2C_CR1 register *******************/
|
||
#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
|
||
#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
|
||
#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
|
||
#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
|
||
#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
|
||
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
|
||
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
|
||
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
|
||
#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
|
||
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
|
||
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
|
||
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
|
||
#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
|
||
#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
|
||
#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
|
||
#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
|
||
#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
|
||
#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
|
||
#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
|
||
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
|
||
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
|
||
|
||
/****************** Bit definition for I2C_CR2 register ********************/
|
||
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
|
||
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
|
||
#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
|
||
#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
|
||
#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
|
||
#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
|
||
#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
|
||
#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
|
||
#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
|
||
#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
|
||
#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
|
||
|
||
/******************* Bit definition for I2C_OAR1 register ******************/
|
||
#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
|
||
#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
|
||
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
|
||
|
||
/******************* Bit definition for I2C_OAR2 register ******************/
|
||
#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
|
||
#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
|
||
#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
|
||
|
||
/******************* Bit definition for I2C_TIMINGR register ****************/
|
||
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
|
||
#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
|
||
#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
|
||
#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
|
||
#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
|
||
|
||
/******************* Bit definition for I2C_TIMEOUTR register ****************/
|
||
#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
|
||
#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
|
||
#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
|
||
#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
|
||
#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
|
||
|
||
/****************** Bit definition for I2C_ISR register ********************/
|
||
#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
|
||
#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
|
||
#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
|
||
#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
|
||
#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
|
||
#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
|
||
#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
|
||
#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
|
||
#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
|
||
#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
|
||
#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
|
||
#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
|
||
#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
|
||
#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
|
||
#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
|
||
#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
|
||
#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
|
||
|
||
/****************** Bit definition for I2C_ICR register ********************/
|
||
#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
|
||
#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
|
||
#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
|
||
#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
|
||
#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
|
||
#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
|
||
#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
|
||
#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
|
||
#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
|
||
|
||
/****************** Bit definition for I2C_PECR register *******************/
|
||
#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
|
||
|
||
/****************** Bit definition for I2C_RXDR register *********************/
|
||
#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
|
||
|
||
/****************** Bit definition for I2C_TXDR register *******************/
|
||
#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* Independent WATCHDOG (IWDG) */
|
||
/* */
|
||
/*****************************************************************************/
|
||
/******************* Bit definition for IWDG_KR register *******************/
|
||
#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
|
||
|
||
/******************* Bit definition for IWDG_PR register *******************/
|
||
#define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
|
||
#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
|
||
#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
|
||
#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
|
||
|
||
/******************* Bit definition for IWDG_RLR register ******************/
|
||
#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
|
||
|
||
/******************* Bit definition for IWDG_SR register *******************/
|
||
#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
|
||
#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
|
||
#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
|
||
|
||
/******************* Bit definition for IWDG_KR register *******************/
|
||
#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* Power Control (PWR) */
|
||
/* */
|
||
/*****************************************************************************/
|
||
|
||
/******************** Bit definition for PWR_CR register *******************/
|
||
#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
|
||
#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
|
||
#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
|
||
#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
|
||
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
|
||
|
||
/******************* Bit definition for PWR_CSR register *******************/
|
||
#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
|
||
#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
|
||
#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
|
||
|
||
#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
|
||
#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
|
||
#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
|
||
#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
|
||
#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
|
||
#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
|
||
#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
|
||
#define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* Reset and Clock Control */
|
||
/* */
|
||
/*****************************************************************************/
|
||
|
||
/******************** Bit definition for RCC_CR register *******************/
|
||
#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
|
||
#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
|
||
|
||
#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
|
||
#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
||
#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
||
#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
||
#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
|
||
#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
|
||
|
||
#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
|
||
#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||
#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||
#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||
#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||
#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||
#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||
|
||
#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
|
||
#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
|
||
#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
|
||
#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
|
||
#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
|
||
#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
|
||
|
||
/******************** Bit definition for RCC_CFGR register *****************/
|
||
/*!< SW configuration */
|
||
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
|
||
#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||
#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||
|
||
#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
|
||
#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
|
||
#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
|
||
#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
|
||
|
||
/*!< SWS configuration */
|
||
#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
||
#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
|
||
#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
|
||
|
||
#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
|
||
#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
|
||
#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
|
||
#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
|
||
|
||
/*!< HPRE configuration */
|
||
#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
|
||
#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
||
#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
||
#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
||
#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
||
|
||
#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
|
||
#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
|
||
#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
|
||
#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
|
||
#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
|
||
#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
|
||
#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
|
||
#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
|
||
#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
|
||
|
||
/*!< PPRE configuration */
|
||
#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
|
||
#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
||
#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
||
#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
||
|
||
#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
||
#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
|
||
#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
|
||
#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
|
||
#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
|
||
|
||
/*!< ADCPPRE configuration */
|
||
#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
|
||
|
||
#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
|
||
#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
|
||
|
||
#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
|
||
#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
||
#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
|
||
#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
|
||
#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
|
||
|
||
#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
|
||
#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
|
||
#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
|
||
|
||
/*!< PLLMUL configuration */
|
||
#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
|
||
#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
|
||
#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
|
||
#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
|
||
#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
|
||
|
||
#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
|
||
#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
|
||
#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
|
||
#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
|
||
#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
|
||
#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
|
||
#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
|
||
#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
|
||
#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
|
||
#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
|
||
#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
|
||
#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
|
||
#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
|
||
#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
|
||
#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
|
||
|
||
/*!< USB configuration */
|
||
#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
|
||
|
||
/*!< MCO configuration */
|
||
#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
|
||
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
||
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
||
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
||
#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
|
||
|
||
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
||
#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
|
||
#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
|
||
#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
|
||
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
|
||
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
|
||
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
|
||
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
||
#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
|
||
|
||
#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
|
||
#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
|
||
#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
|
||
#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
|
||
#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
|
||
#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
|
||
#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
|
||
#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
|
||
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
|
||
|
||
#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
|
||
|
||
/*!<****************** Bit definition for RCC_CIR register *****************/
|
||
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
|
||
#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
|
||
#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
|
||
#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
|
||
#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
|
||
#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
|
||
#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
|
||
#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
|
||
#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
|
||
#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
|
||
#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
|
||
#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
|
||
#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
|
||
#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
|
||
#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
|
||
#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
|
||
#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
|
||
#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
|
||
#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
|
||
#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
|
||
#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
|
||
#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
|
||
#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
|
||
|
||
/***************** Bit definition for RCC_APB2RSTR register ****************/
|
||
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
|
||
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
|
||
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
|
||
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
|
||
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
|
||
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
|
||
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
|
||
#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
|
||
|
||
/*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
|
||
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
|
||
|
||
/***************** Bit definition for RCC_APB1RSTR register ****************/
|
||
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
|
||
#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
|
||
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
|
||
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
|
||
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
|
||
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
|
||
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
|
||
#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
|
||
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
|
||
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
|
||
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
|
||
#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
|
||
#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
|
||
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
|
||
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
|
||
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
|
||
|
||
/****************** Bit definition for RCC_AHBENR register *****************/
|
||
#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
|
||
#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
|
||
#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
|
||
#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
|
||
#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
|
||
#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
|
||
#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
|
||
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
|
||
#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
|
||
|
||
/* Old Bit definition maintained for legacy purpose */
|
||
#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
|
||
#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
|
||
|
||
/***************** Bit definition for RCC_APB2ENR register *****************/
|
||
#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
|
||
#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
|
||
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
|
||
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
|
||
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
|
||
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
|
||
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
|
||
#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
|
||
|
||
/* Old Bit definition maintained for legacy purpose */
|
||
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
|
||
#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
|
||
|
||
/***************** Bit definition for RCC_APB1ENR register *****************/
|
||
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
|
||
#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
|
||
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
|
||
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
|
||
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
|
||
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
|
||
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
|
||
#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
|
||
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
|
||
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
|
||
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
|
||
#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
|
||
#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
|
||
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
|
||
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
|
||
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
|
||
|
||
/******************* Bit definition for RCC_BDCR register ******************/
|
||
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
|
||
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
|
||
#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
|
||
|
||
#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
|
||
#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
||
#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
||
|
||
#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
|
||
#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
||
#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
||
|
||
/*!< RTC configuration */
|
||
#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
||
#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
|
||
#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
|
||
#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
|
||
|
||
#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
|
||
#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
|
||
|
||
/******************* Bit definition for RCC_CSR register *******************/
|
||
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
|
||
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
|
||
#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
|
||
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
|
||
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
|
||
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
|
||
#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
|
||
#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
|
||
#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
|
||
#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
|
||
#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
|
||
|
||
/* Old Bit definition maintained for legacy purpose */
|
||
#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
|
||
|
||
/******************* Bit definition for RCC_AHBRSTR register ***************/
|
||
#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
|
||
#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
|
||
#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
|
||
#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
|
||
#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
|
||
|
||
/* Old Bit definition maintained for legacy purpose */
|
||
#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
|
||
|
||
/******************* Bit definition for RCC_CFGR2 register *****************/
|
||
/*!< PREDIV configuration */
|
||
#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
|
||
#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||
#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||
#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||
#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||
|
||
#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
|
||
#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
|
||
#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
|
||
#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
|
||
#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
|
||
#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
|
||
#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
|
||
#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
|
||
#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
|
||
#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
|
||
#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
|
||
#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
|
||
#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
|
||
#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
|
||
#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
|
||
#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
|
||
|
||
/******************* Bit definition for RCC_CFGR3 register *****************/
|
||
/*!< USART1 Clock source selection */
|
||
#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
|
||
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||
|
||
#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
|
||
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
|
||
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
|
||
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
|
||
|
||
/*!< I2C1 Clock source selection */
|
||
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
|
||
|
||
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
|
||
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
|
||
|
||
/*!< CEC Clock source selection */
|
||
#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
|
||
|
||
#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
|
||
#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
|
||
|
||
/*!< USB Clock source selection */
|
||
#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
|
||
|
||
#define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
|
||
#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
|
||
|
||
/******************* Bit definition for RCC_CR2 register *******************/
|
||
#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
|
||
#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
|
||
#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
|
||
#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
|
||
#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
|
||
#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
|
||
#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
|
||
#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* Real-Time Clock (RTC) */
|
||
/* */
|
||
/*****************************************************************************/
|
||
/******************** Bits definition for RTC_TR register ******************/
|
||
#define RTC_TR_PM ((uint32_t)0x00400000)
|
||
#define RTC_TR_HT ((uint32_t)0x00300000)
|
||
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
|
||
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
|
||
#define RTC_TR_HU ((uint32_t)0x000F0000)
|
||
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
|
||
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
|
||
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
|
||
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
|
||
#define RTC_TR_MNT ((uint32_t)0x00007000)
|
||
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
|
||
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
|
||
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
|
||
#define RTC_TR_MNU ((uint32_t)0x00000F00)
|
||
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
|
||
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
|
||
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
|
||
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
|
||
#define RTC_TR_ST ((uint32_t)0x00000070)
|
||
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
|
||
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
|
||
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
|
||
#define RTC_TR_SU ((uint32_t)0x0000000F)
|
||
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
|
||
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
|
||
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
|
||
#define RTC_TR_SU_3 ((uint32_t)0x00000008)
|
||
|
||
/******************** Bits definition for RTC_DR register ******************/
|
||
#define RTC_DR_YT ((uint32_t)0x00F00000)
|
||
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
|
||
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
|
||
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
|
||
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
|
||
#define RTC_DR_YU ((uint32_t)0x000F0000)
|
||
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
|
||
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
|
||
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
|
||
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
|
||
#define RTC_DR_WDU ((uint32_t)0x0000E000)
|
||
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
|
||
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
|
||
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
|
||
#define RTC_DR_MT ((uint32_t)0x00001000)
|
||
#define RTC_DR_MU ((uint32_t)0x00000F00)
|
||
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
|
||
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
|
||
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
|
||
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
|
||
#define RTC_DR_DT ((uint32_t)0x00000030)
|
||
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
|
||
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
|
||
#define RTC_DR_DU ((uint32_t)0x0000000F)
|
||
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
|
||
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
|
||
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
|
||
#define RTC_DR_DU_3 ((uint32_t)0x00000008)
|
||
|
||
/******************** Bits definition for RTC_CR register ******************/
|
||
#define RTC_CR_COE ((uint32_t)0x00800000)
|
||
#define RTC_CR_OSEL ((uint32_t)0x00600000)
|
||
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
|
||
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
|
||
#define RTC_CR_POL ((uint32_t)0x00100000)
|
||
#define RTC_CR_COSEL ((uint32_t)0x00080000)
|
||
#define RTC_CR_BCK ((uint32_t)0x00040000)
|
||
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
|
||
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
|
||
#define RTC_CR_TSIE ((uint32_t)0x00008000)
|
||
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
|
||
#define RTC_CR_TSE ((uint32_t)0x00000800)
|
||
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
|
||
#define RTC_CR_FMT ((uint32_t)0x00000040)
|
||
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
|
||
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
|
||
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
|
||
|
||
/******************** Bits definition for RTC_ISR register *****************/
|
||
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
|
||
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
|
||
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
|
||
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
|
||
#define RTC_ISR_TSF ((uint32_t)0x00000800)
|
||
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
|
||
#define RTC_ISR_INIT ((uint32_t)0x00000080)
|
||
#define RTC_ISR_INITF ((uint32_t)0x00000040)
|
||
#define RTC_ISR_RSF ((uint32_t)0x00000020)
|
||
#define RTC_ISR_INITS ((uint32_t)0x00000010)
|
||
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
|
||
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
|
||
|
||
/******************** Bits definition for RTC_PRER register ****************/
|
||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||
|
||
/******************** Bits definition for RTC_ALRMAR register **************/
|
||
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
|
||
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
|
||
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
|
||
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
|
||
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
|
||
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
|
||
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
|
||
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
|
||
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
|
||
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
|
||
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
|
||
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
|
||
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
|
||
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
|
||
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
|
||
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
|
||
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
|
||
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
|
||
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
|
||
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
|
||
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
|
||
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
|
||
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
|
||
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
|
||
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
|
||
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
|
||
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
|
||
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
|
||
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
|
||
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
|
||
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
|
||
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
|
||
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
|
||
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
|
||
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
|
||
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
|
||
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
|
||
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
|
||
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
|
||
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
|
||
|
||
/******************** Bits definition for RTC_WPR register *****************/
|
||
#define RTC_WPR_KEY ((uint32_t)0x000000FF)
|
||
|
||
/******************** Bits definition for RTC_SSR register *****************/
|
||
#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
|
||
|
||
/******************** Bits definition for RTC_SHIFTR register **************/
|
||
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
|
||
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
|
||
|
||
/******************** Bits definition for RTC_TSTR register ****************/
|
||
#define RTC_TSTR_PM ((uint32_t)0x00400000)
|
||
#define RTC_TSTR_HT ((uint32_t)0x00300000)
|
||
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
|
||
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
|
||
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
|
||
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
|
||
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
|
||
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
|
||
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
|
||
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
|
||
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
|
||
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
|
||
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
|
||
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
|
||
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
|
||
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
|
||
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
|
||
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
|
||
#define RTC_TSTR_ST ((uint32_t)0x00000070)
|
||
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
|
||
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
|
||
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
|
||
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
|
||
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
|
||
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
|
||
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
|
||
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
|
||
|
||
/******************** Bits definition for RTC_TSDR register ****************/
|
||
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
|
||
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
|
||
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
|
||
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
|
||
#define RTC_TSDR_MT ((uint32_t)0x00001000)
|
||
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
|
||
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
|
||
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
|
||
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
|
||
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
|
||
#define RTC_TSDR_DT ((uint32_t)0x00000030)
|
||
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
|
||
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
|
||
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
|
||
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
|
||
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
|
||
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
|
||
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
|
||
|
||
/******************** Bits definition for RTC_TSSSR register ***************/
|
||
#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
|
||
|
||
/******************** Bits definition for RTC_CALR register ****************/
|
||
#define RTC_CALR_CALP ((uint32_t)0x00008000)
|
||
#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
|
||
#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
|
||
#define RTC_CALR_CALM ((uint32_t)0x000001FF)
|
||
#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
|
||
#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
|
||
#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
|
||
#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
|
||
#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
|
||
#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
|
||
#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
|
||
#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
|
||
#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
|
||
|
||
/******************** Bits definition for RTC_TAFCR register ***************/
|
||
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
|
||
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
|
||
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
|
||
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
|
||
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
|
||
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
|
||
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
|
||
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
|
||
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
|
||
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
|
||
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
|
||
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
|
||
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
|
||
#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
|
||
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
|
||
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
|
||
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
|
||
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
|
||
|
||
/******************** Bits definition for RTC_ALRMASSR register ************/
|
||
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
|
||
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
|
||
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
|
||
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
|
||
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
|
||
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
|
||
|
||
/******************** Bits definition for RTC_BKP0R register ***************/
|
||
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
|
||
|
||
/******************** Bits definition for RTC_BKP1R register ***************/
|
||
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
|
||
|
||
/******************** Bits definition for RTC_BKP2R register ***************/
|
||
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
|
||
|
||
/******************** Bits definition for RTC_BKP3R register ***************/
|
||
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
|
||
|
||
/******************** Bits definition for RTC_BKP4R register ***************/
|
||
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
||
|
||
/******************** Number of backup registers ******************************/
|
||
#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* Serial Peripheral Interface (SPI) */
|
||
/* */
|
||
/*****************************************************************************/
|
||
/******************* Bit definition for SPI_CR1 register *******************/
|
||
#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
|
||
#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
|
||
#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
|
||
#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
|
||
#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
|
||
#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
|
||
#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
|
||
#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
|
||
#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
|
||
#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
|
||
#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
|
||
#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
|
||
#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
|
||
#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
|
||
#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
|
||
#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
|
||
#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
|
||
|
||
/******************* Bit definition for SPI_CR2 register *******************/
|
||
#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
|
||
#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
|
||
#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
|
||
#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
|
||
#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
|
||
#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
|
||
#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
|
||
#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
|
||
#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
|
||
#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
|
||
#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
|
||
#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
|
||
#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
|
||
#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
|
||
#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
|
||
#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
|
||
|
||
/******************** Bit definition for SPI_SR register *******************/
|
||
#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
|
||
#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
|
||
#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
|
||
#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
|
||
#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
|
||
#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
|
||
#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
|
||
#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
|
||
#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
|
||
#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
|
||
#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
|
||
#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
|
||
#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
|
||
#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
|
||
#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
|
||
|
||
/******************** Bit definition for SPI_DR register *******************/
|
||
#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
|
||
|
||
/******************* Bit definition for SPI_CRCPR register *****************/
|
||
#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
|
||
|
||
/****************** Bit definition for SPI_RXCRCR register *****************/
|
||
#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
|
||
|
||
/****************** Bit definition for SPI_TXCRCR register *****************/
|
||
#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
|
||
|
||
/****************** Bit definition for SPI_I2SCFGR register ****************/
|
||
#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
|
||
#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
|
||
#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
||
#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
||
#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
|
||
#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
|
||
#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
|
||
#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
|
||
#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
|
||
#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
|
||
|
||
/****************** Bit definition for SPI_I2SPR register ******************/
|
||
#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
|
||
#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
|
||
#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* System Configuration (SYSCFG) */
|
||
/* */
|
||
/*****************************************************************************/
|
||
/***************** Bit definition for SYSCFG_CFGR1 register ****************/
|
||
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
|
||
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
|
||
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
|
||
|
||
#define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages */
|
||
|
||
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
|
||
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
|
||
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
|
||
#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
|
||
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
|
||
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
|
||
|
||
#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
|
||
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
|
||
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
|
||
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
|
||
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
|
||
#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
|
||
#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
|
||
#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
|
||
|
||
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
|
||
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
|
||
#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
|
||
#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
|
||
#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
|
||
|
||
/**
|
||
* @brief EXTI0 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
|
||
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
|
||
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
|
||
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
|
||
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
|
||
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
|
||
|
||
/**
|
||
* @brief EXTI1 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
|
||
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
|
||
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
|
||
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
|
||
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
|
||
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
|
||
|
||
/**
|
||
* @brief EXTI2 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
|
||
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
|
||
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
|
||
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
|
||
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
|
||
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
|
||
|
||
/**
|
||
* @brief EXTI3 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
|
||
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
|
||
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
|
||
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
|
||
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
|
||
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
|
||
|
||
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
|
||
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
|
||
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
|
||
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
|
||
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
|
||
|
||
/**
|
||
* @brief EXTI4 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
|
||
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
|
||
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
|
||
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
|
||
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
|
||
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
|
||
|
||
/**
|
||
* @brief EXTI5 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
|
||
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
|
||
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
|
||
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
|
||
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
|
||
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
|
||
|
||
/**
|
||
* @brief EXTI6 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
|
||
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
|
||
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
|
||
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
|
||
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
|
||
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
|
||
|
||
/**
|
||
* @brief EXTI7 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
|
||
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
|
||
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
|
||
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
|
||
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
|
||
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
|
||
|
||
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
|
||
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
|
||
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
|
||
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
|
||
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
|
||
|
||
/**
|
||
* @brief EXTI8 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
|
||
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
|
||
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
|
||
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
|
||
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
|
||
|
||
/**
|
||
* @brief EXTI9 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
|
||
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
|
||
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
|
||
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
|
||
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
|
||
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
|
||
|
||
/**
|
||
* @brief EXTI10 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
|
||
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
|
||
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
|
||
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
|
||
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
|
||
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
|
||
|
||
/**
|
||
* @brief EXTI11 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
|
||
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
|
||
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
|
||
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
|
||
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
|
||
|
||
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
|
||
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
|
||
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
|
||
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
|
||
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
|
||
|
||
/**
|
||
* @brief EXTI12 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
|
||
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
|
||
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
|
||
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
|
||
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
|
||
|
||
/**
|
||
* @brief EXTI13 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
|
||
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
|
||
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
|
||
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
|
||
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
|
||
|
||
/**
|
||
* @brief EXTI14 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
|
||
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
|
||
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
|
||
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
|
||
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
|
||
|
||
/**
|
||
* @brief EXTI15 configuration
|
||
*/
|
||
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
|
||
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
|
||
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
|
||
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
|
||
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
|
||
|
||
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
|
||
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
|
||
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
|
||
#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
|
||
#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
|
||
|
||
/*****************************************************************************/
|
||
/* */
|
||
/* Timers (TIM) */
|
||
/* */
|
||
/*****************************************************************************/
|
||
/******************* Bit definition for TIM_CR1 register *******************/
|
||
#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
|
||
#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
|
||
#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
|
||
#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
|
||
#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
|
||
|
||
#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
||
#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
||
#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
||
|
||
#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
|
||
|
||
#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
|
||
#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
|
||
/******************* Bit definition for TIM_CR2 register *******************/
|
||
#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
|
||
#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
|
||
#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
|
||
|
||
#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
|
||
#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
|
||
#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
|
||
#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
|
||
#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
|
||
#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
|
||
#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
|
||
#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
|
||
#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
|
||
#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
|
||
|
||
/******************* Bit definition for TIM_SMCR register ******************/
|
||
#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
|
||
#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||
#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||
#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
||
|
||
#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
|
||
|
||
#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
|
||
#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
|
||
#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
|
||
|
||
#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
|
||
#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||
#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||
|
||
#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
||
#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
||
#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
||
|
||
#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
|
||
#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
|
||
|
||
/******************* Bit definition for TIM_DIER register ******************/
|
||
#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
|
||
#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
|
||
#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
|
||
#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
|
||
#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
|
||
#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
|
||
#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
|
||
#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
|
||
#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
|
||
#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
|
||
#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
|
||
#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
|
||
#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
|
||
#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
|
||
#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
|
||
|
||
/******************** Bit definition for TIM_SR register *******************/
|
||
#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
|
||
#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
|
||
#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
|
||
#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
|
||
#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
|
||
#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
|
||
#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
|
||
#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
|
||
#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
|
||
#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
|
||
#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
|
||
#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
|
||
|
||
/******************* Bit definition for TIM_EGR register *******************/
|
||
#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
|
||
#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
|
||
#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
|
||
#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
|
||
#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
|
||
#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
|
||
#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
|
||
#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
|
||
|
||
/****************** Bit definition for TIM_CCMR1 register ******************/
|
||
#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
||
#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||
#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
|
||
#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
|
||
|
||
#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
||
#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
|
||
#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
|
||
|
||
#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
||
#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
|
||
#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
|
||
|
||
#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
||
#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
||
#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
||
#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
||
|
||
#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
|
||
|
||
/*---------------------------------------------------------------------------*/
|
||
|
||
#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
||
#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
||
#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
||
#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||
|
||
#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
||
#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
||
#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
||
#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
||
#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
||
#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
||
#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
|
||
|
||
/****************** Bit definition for TIM_CCMR2 register ******************/
|
||
#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
||
#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||
#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
|
||
#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
|
||
|
||
#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
||
#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
|
||
#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
|
||
|
||
#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
||
#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
|
||
#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
|
||
|
||
#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
||
#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
||
#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
||
#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
||
|
||
#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
|
||
|
||
/*---------------------------------------------------------------------------*/
|
||
|
||
#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
||
#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
||
#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
||
#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
||
#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
||
#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||
#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||
|
||
#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
||
#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
||
#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
||
|
||
#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
||
#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
||
#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
||
#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
||
#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
|
||
|
||
/******************* Bit definition for TIM_CCER register ******************/
|
||
#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
|
||
#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
|
||
#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
|
||
#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
|
||
#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
|
||
#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
|
||
#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
|
||
#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
|
||
#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
|
||
#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
|
||
#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
|
||
#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
|
||
#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
|
||
#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
|
||
#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
|
||
|
||
/******************* Bit definition for TIM_CNT register *******************/
|
||
#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
|
||
|
||
/******************* Bit definition for TIM_PSC register *******************/
|
||
#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
|
||
|
||
/******************* Bit definition for TIM_ARR register *******************/
|
||
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
|
||
|
||
/******************* Bit definition for TIM_RCR register *******************/
|
||
#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
|
||
|
||
/******************* Bit definition for TIM_CCR1 register ******************/
|
||
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
|
||
|
||
/******************* Bit definition for TIM_CCR2 register ******************/
|
||
#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
|
||
|
||
/******************* Bit definition for TIM_CCR3 register ******************/
|
||
#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
|
||
|
||
/******************* Bit definition for TIM_CCR4 register ******************/
|
||
#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
|
||
|
||
/******************* Bit definition for TIM_BDTR register ******************/
|
||
#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
||
#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||
#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||
#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
||
#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
||
#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
||
#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
||
#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
||
#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
||
|
||
#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
|
||
#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
|
||
#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
|
||
#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
|
||
#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
|
||
#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
|
||
#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
|
||
#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
|
||
|
||
/******************* Bit definition for TIM_DCR register *******************/
|
||
#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
|
||
#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||
#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||
#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
||
#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
||
#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
||
|
||
#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
|
||
#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||
#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||
#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||
#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||
#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||
|
||
/******************* Bit definition for TIM_DMAR register ******************/
|
||
#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
|
||
|
||
/******************* Bit definition for TIM14_OR register ********************/
|
||
#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
|
||
#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
||
#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Touch Sensing Controller (TSC) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************* Bit definition for TSC_CR register *********************/
|
||
#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
|
||
#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
|
||
#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
|
||
#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
|
||
#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
|
||
|
||
#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
|
||
#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
||
#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
||
#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
||
|
||
#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
|
||
#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
||
#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
||
#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
||
|
||
#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
|
||
#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
|
||
|
||
#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
|
||
#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
||
#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
||
#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
||
#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
||
#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
|
||
#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
|
||
#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
|
||
|
||
#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
|
||
#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
||
#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
||
#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
||
#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
||
|
||
#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
|
||
#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
||
#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
||
#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
|
||
#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
|
||
|
||
/******************* Bit definition for TSC_IER register ********************/
|
||
#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
|
||
#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
|
||
|
||
/******************* Bit definition for TSC_ICR register ********************/
|
||
#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
|
||
#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
|
||
|
||
/******************* Bit definition for TSC_ISR register ********************/
|
||
#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
|
||
#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
|
||
|
||
/******************* Bit definition for TSC_IOHCR register ******************/
|
||
#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
|
||
#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
|
||
|
||
/******************* Bit definition for TSC_IOASCR register *****************/
|
||
#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
|
||
#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
|
||
#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
|
||
#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
|
||
#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
|
||
|
||
/******************* Bit definition for TSC_IOSCR register ******************/
|
||
#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
|
||
#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
|
||
#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
|
||
#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
|
||
#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
|
||
#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
|
||
#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
|
||
#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
|
||
#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
|
||
#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
|
||
#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
|
||
#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
|
||
#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
|
||
#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
|
||
#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
|
||
#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
|
||
#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
|
||
#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
|
||
#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
|
||
#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
|
||
#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
|
||
#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
|
||
#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
|
||
#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
|
||
#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
|
||
#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
|
||
#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
|
||
#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
|
||
#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
|
||
#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
|
||
#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
|
||
#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
|
||
|
||
/******************* Bit definition for TSC_IOCCR register ******************/
|
||
#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
|
||
#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
|
||
#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
|
||
#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
|
||
#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
|
||
#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
|
||
#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
|
||
#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
|
||
#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
|
||
#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
|
||
#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
|
||
#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
|
||
#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
|
||
#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
|
||
#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
|
||
#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
|
||
#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
|
||
#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
|
||
#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
|
||
#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
|
||
#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
|
||
#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
|
||
#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
|
||
#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
|
||
#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
|
||
#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
|
||
#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
|
||
#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
|
||
#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
|
||
#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
|
||
#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
|
||
#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
|
||
|
||
/******************* Bit definition for TSC_IOGCSR register *****************/
|
||
#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
|
||
#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
|
||
#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
|
||
#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
|
||
#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
|
||
#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
|
||
#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
|
||
#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
|
||
#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
|
||
#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
|
||
#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
|
||
#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
|
||
#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
|
||
#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
|
||
#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
|
||
#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
|
||
|
||
/******************* Bit definition for TSC_IOGXCR register *****************/
|
||
#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/****************** Bit definition for USART_CR1 register *******************/
|
||
#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
|
||
#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
|
||
#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
|
||
#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
|
||
#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
|
||
#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
|
||
#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
|
||
#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
|
||
#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
|
||
#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
|
||
#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
|
||
#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
|
||
#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
|
||
#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
|
||
#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
|
||
#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
|
||
#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
|
||
#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
|
||
#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
|
||
#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
|
||
#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
|
||
#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
|
||
#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
|
||
#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
|
||
#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
|
||
#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
|
||
#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
|
||
#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
|
||
#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
|
||
#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
|
||
#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
|
||
#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
|
||
|
||
/****************** Bit definition for USART_CR2 register *******************/
|
||
#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
|
||
#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
|
||
#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
|
||
#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
|
||
#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
|
||
#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
|
||
#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
|
||
#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
|
||
#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
|
||
#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
|
||
#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
|
||
#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
|
||
#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
|
||
#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
|
||
#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
|
||
#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
|
||
#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
|
||
#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
|
||
#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
|
||
#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
|
||
#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
|
||
#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
|
||
|
||
/****************** Bit definition for USART_CR3 register *******************/
|
||
#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
|
||
#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
|
||
#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
|
||
#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
|
||
#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
|
||
#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
|
||
#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
|
||
#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
|
||
#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
|
||
#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
|
||
#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
|
||
#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
|
||
#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
|
||
#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
|
||
#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
|
||
#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
|
||
#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
|
||
#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
|
||
#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
|
||
#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
|
||
#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
|
||
#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
|
||
#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
|
||
#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
|
||
|
||
/****************** Bit definition for USART_BRR register *******************/
|
||
#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
|
||
#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
|
||
|
||
/****************** Bit definition for USART_GTPR register ******************/
|
||
#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
|
||
#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
|
||
|
||
|
||
/******************* Bit definition for USART_RTOR register *****************/
|
||
#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
|
||
#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
|
||
|
||
/******************* Bit definition for USART_RQR register ******************/
|
||
#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
|
||
#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
|
||
#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
|
||
#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
|
||
#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
|
||
|
||
/******************* Bit definition for USART_ISR register ******************/
|
||
#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
|
||
#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
|
||
#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
|
||
#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
|
||
#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
|
||
#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
|
||
#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
|
||
#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
|
||
#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
|
||
#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
|
||
#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
|
||
#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
|
||
#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
|
||
#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
|
||
#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
|
||
#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
|
||
#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
|
||
#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
|
||
#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
|
||
#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
|
||
#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
|
||
#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
|
||
|
||
/******************* Bit definition for USART_ICR register ******************/
|
||
#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
|
||
#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
|
||
#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
|
||
#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
|
||
#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
|
||
#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
|
||
#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
|
||
#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
|
||
#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
|
||
#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
|
||
#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
|
||
#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
|
||
|
||
/******************* Bit definition for USART_RDR register ******************/
|
||
#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
|
||
|
||
/******************* Bit definition for USART_TDR register ******************/
|
||
#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* USB Device General registers */
|
||
/* */
|
||
/******************************************************************************/
|
||
#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
|
||
#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
|
||
#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
|
||
#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
|
||
#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
|
||
#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
|
||
#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
|
||
|
||
/**************************** ISTR interrupt events *************************/
|
||
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
|
||
#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
|
||
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
|
||
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
|
||
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
|
||
#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
|
||
#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
|
||
#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
|
||
#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
|
||
#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
|
||
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
|
||
|
||
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
|
||
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
|
||
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
|
||
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
|
||
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
|
||
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
|
||
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
|
||
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
|
||
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
|
||
|
||
/************************* CNTR control register bits definitions ***********/
|
||
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
|
||
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
|
||
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
|
||
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
|
||
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
|
||
#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
|
||
#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
|
||
#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
|
||
#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
|
||
#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
|
||
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
|
||
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
|
||
#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
|
||
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
|
||
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
|
||
|
||
/************************* BCDR control register bits definitions ***********/
|
||
#define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
|
||
#define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
|
||
#define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
|
||
#define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
|
||
#define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
|
||
#define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
|
||
#define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
|
||
#define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
|
||
#define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
|
||
|
||
/*************************** LPM register bits definitions ******************/
|
||
#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
|
||
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
|
||
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
|
||
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
|
||
|
||
/******************** FNR Frame Number Register bit definitions ************/
|
||
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
|
||
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
|
||
#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
|
||
#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
|
||
#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
|
||
|
||
/******************** DADDR Device ADDRess bit definitions ****************/
|
||
#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
|
||
#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
|
||
|
||
/****************************** Endpoint register *************************/
|
||
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
|
||
#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
|
||
#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
|
||
#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
|
||
#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
|
||
#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
|
||
#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
|
||
#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
|
||
/* bit positions */
|
||
#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
|
||
#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
|
||
#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
|
||
#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
|
||
#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
|
||
#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
|
||
#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
|
||
#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
|
||
#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
|
||
#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
|
||
|
||
/* EndPoint REGister MASK (no toggle fields) */
|
||
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
|
||
/*!< EP_TYPE[1:0] EndPoint TYPE */
|
||
#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
|
||
#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
|
||
#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
|
||
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
|
||
#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
|
||
#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
|
||
|
||
#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
|
||
/*!< STAT_TX[1:0] STATus for TX transfer */
|
||
#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
|
||
#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
|
||
#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
|
||
#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
|
||
#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
|
||
#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
|
||
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
|
||
/*!< STAT_RX[1:0] STATus for RX transfer */
|
||
#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
|
||
#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
|
||
#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
|
||
#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
|
||
#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
|
||
#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
|
||
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
|
||
|
||
/******************************************************************************/
|
||
/* */
|
||
/* Window WATCHDOG (WWDG) */
|
||
/* */
|
||
/******************************************************************************/
|
||
/******************* Bit definition for WWDG_CR register ********************/
|
||
#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
||
#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
|
||
#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
|
||
#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
|
||
#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
|
||
#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
|
||
#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
|
||
#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
|
||
|
||
#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
|
||
|
||
/******************* Bit definition for WWDG_CFR register *******************/
|
||
#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
|
||
#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
|
||
#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
|
||
#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
|
||
#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
|
||
#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
|
||
#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
|
||
#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
|
||
|
||
#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
|
||
#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
|
||
#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
|
||
|
||
#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
|
||
|
||
/******************* Bit definition for WWDG_SR register ********************/
|
||
#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
|
||
/** @addtogroup Exported_macro
|
||
* @{
|
||
*/
|
||
|
||
/****************************** ADC Instances *********************************/
|
||
#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
||
|
||
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
|
||
|
||
/******************************* CAN Instances ********************************/
|
||
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
|
||
|
||
/****************************** CEC Instances *********************************/
|
||
#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
|
||
|
||
/****************************** CRC Instances *********************************/
|
||
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
||
|
||
/******************************* DMA Instances ******************************/
|
||
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
||
((INSTANCE) == DMA1_Channel2) || \
|
||
((INSTANCE) == DMA1_Channel3) || \
|
||
((INSTANCE) == DMA1_Channel4) || \
|
||
((INSTANCE) == DMA1_Channel5))
|
||
|
||
/****************************** GPIO Instances ********************************/
|
||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||
((INSTANCE) == GPIOB) || \
|
||
((INSTANCE) == GPIOC) || \
|
||
((INSTANCE) == GPIOF))
|
||
|
||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||
((INSTANCE) == GPIOB) || \
|
||
((INSTANCE) == GPIOF))
|
||
|
||
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||
((INSTANCE) == GPIOB))
|
||
|
||
/****************************** I2C Instances *********************************/
|
||
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||
|
||
/****************************** I2S Instances *********************************/
|
||
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
|
||
|
||
/****************************** IWDG Instances ********************************/
|
||
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
||
|
||
/****************************** RTC Instances *********************************/
|
||
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
||
|
||
/****************************** SMBUS Instances *********************************/
|
||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||
|
||
/****************************** SPI Instances *********************************/
|
||
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
||
((INSTANCE) == SPI2))
|
||
|
||
/****************************** TIM Instances *********************************/
|
||
#define IS_TIM_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3) || \
|
||
((INSTANCE) == TIM14) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3) || \
|
||
((INSTANCE) == TIM14) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_CC2_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CC3_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CC4_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1))
|
||
|
||
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1))
|
||
|
||
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1))
|
||
|
||
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
|
||
((INSTANCE) == TIM2)
|
||
|
||
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
||
((((INSTANCE) == TIM1) && \
|
||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||
|| \
|
||
(((INSTANCE) == TIM2) && \
|
||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||
|| \
|
||
(((INSTANCE) == TIM3) && \
|
||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||
((CHANNEL) == TIM_CHANNEL_3) || \
|
||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||
|| \
|
||
(((INSTANCE) == TIM16) && \
|
||
(((CHANNEL) == TIM_CHANNEL_1))) \
|
||
|| \
|
||
(((INSTANCE) == TIM17) && \
|
||
(((CHANNEL) == TIM_CHANNEL_1))))
|
||
|
||
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
|
||
((((INSTANCE) == TIM1) && \
|
||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||
((CHANNEL) == TIM_CHANNEL_2) || \
|
||
((CHANNEL) == TIM_CHANNEL_3))) \
|
||
|| \
|
||
(((INSTANCE) == TIM16) && \
|
||
((CHANNEL) == TIM_CHANNEL_1)) \
|
||
|| \
|
||
(((INSTANCE) == TIM17) && \
|
||
((CHANNEL) == TIM_CHANNEL_1)))
|
||
|
||
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3))
|
||
|
||
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3) || \
|
||
((INSTANCE) == TIM14) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1))
|
||
|
||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1))
|
||
|
||
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM2) || \
|
||
((INSTANCE) == TIM3) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM16) || \
|
||
((INSTANCE) == TIM17))
|
||
|
||
#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
|
||
(((INSTANCE) == TIM1) || \
|
||
((INSTANCE) == TIM14))
|
||
|
||
/****************************** TSC Instances *********************************/
|
||
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
|
||
|
||
/*********************** UART Instances : IRDA mode ***************************/
|
||
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||
|
||
/********************* UART Instances : Smard card mode ***********************/
|
||
#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||
|
||
/******************** USART Instances : Synchronous mode **********************/
|
||
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||
((INSTANCE) == USART2))
|
||
|
||
/******************** USART Instances : auto Baud rate detection **************/
|
||
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||
|
||
/******************** UART Instances : Asynchronous mode **********************/
|
||
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||
((INSTANCE) == USART2))
|
||
|
||
/******************** UART Instances : Half-Duplex mode **********************/
|
||
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||
((INSTANCE) == USART2))
|
||
|
||
/****************** UART Instances : Hardware Flow control ********************/
|
||
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||
((INSTANCE) == USART2))
|
||
|
||
/****************** UART Instances : LIN mode ********************/
|
||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||
|
||
/****************** UART Instances : wakeup from stop mode ********************/
|
||
#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||
|
||
/****************** UART Instances : Auto Baud Rate detection ********************/
|
||
#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||
|
||
/****************** UART Instances : Driver enable detection ********************/
|
||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
||
((INSTANCE) == USART2))
|
||
/****************************** USB Instances ********************************/
|
||
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
|
||
|
||
/****************************** WWDG Instances ********************************/
|
||
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
|
||
/******************************************************************************/
|
||
/* For a painless codes migration between the STM32F0xx device product */
|
||
/* lines, the aliases defined below are put in place to overcome the */
|
||
/* differences in the interrupt handlers and IRQn definitions. */
|
||
/* No need to update developed interrupt code when moving across */
|
||
/* product lines within the same STM32F0 Family */
|
||
/******************************************************************************/
|
||
|
||
/* Aliases for __IRQn */
|
||
#define PVD_VDDIO2_IRQn VDDIO2_IRQn
|
||
#define RCC_IRQn RCC_CRS_IRQn
|
||
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
|
||
#define ADC1_COMP_IRQn ADC1_IRQn
|
||
|
||
/* Aliases for __IRQHandler */
|
||
#define PVD_VDDIO2_IRQHandler VDDIO2_IRQHandler
|
||
#define RCC_IRQHandler RCC_CRS_IRQHandler
|
||
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
|
||
#define ADC1_COMP_IRQHandler ADC1_IRQHandler
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif /* __cplusplus */
|
||
|
||
#endif /* __STM32F048xx_H */
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|