270 lines
8.5 KiB
C
270 lines
8.5 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file KL2x/hal_lld.h
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* @brief Kinetis KL2x HAL subsystem low level driver header.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "mk20d5.h"
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#include "kinetis_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @name Platform identification
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* @{
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*/
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#define PLATFORM_NAME "Kinetis"
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/** @} */
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/**
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* @brief Maximum system and core clock (f_SYS) frequency.
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*/
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#define KINETIS_SYSCLK_MAX 48000000
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/**
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* @brief Maximum bus clock (f_BUS) frequency.
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*/
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#define KINETIS_BUSCLK_MAX 24000000
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/**
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* @name Internal clock sources
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* @{
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*/
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#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
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#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
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/** @} */
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#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
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#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
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#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
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#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
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#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
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#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
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#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
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#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the MCG/system clock initialization in the HAL.
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*/
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#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
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#define KINETIS_NO_INIT FALSE
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#endif
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/**
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* @brief MCG mode selection.
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*/
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#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
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#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
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#endif
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/**
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* @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
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* @note The allowed range is 1...16.
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* @note The default value is calculated for a 48 MHz system clock
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* from a 96 MHz PLL output.
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*/
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#if !defined(KINETIS_MCG_FLL_OUTDIV1) || defined(__DOXYGEN__)
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#define KINETIS_MCG_FLL_OUTDIV1 2
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#endif
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/**
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* @brief Additional clock divider bus/flash clocks (OUTDIV4).
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* @note The allowed range is 1...8.
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* @note This divider is on top of the OUTDIV1 divider.
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* @note The default value is calculated for 24 MHz bus/flash clocks
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* from a 96 MHz PLL output and 48 MHz core/system clock.
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*/
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#if !defined(KINETIS_MCG_FLL_OUTDIV4) || defined(__DOXYGEN__)
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#define KINETIS_MCG_FLL_OUTDIV4 2
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#endif
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/**
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* @brief FLL DCO tuning enable for 32.768 kHz reference.
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* @note Set to 1 for fine-tuning DCO for maximum frequency with
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* a 32.768 kHz reference.
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* @note The default value is for a 32.768 kHz external crystal.
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*/
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#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
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#define KINETIS_MCG_FLL_DMX32 1
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#endif
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/**
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* @brief FLL DCO range selection.
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* @note The allowed range is 0...3.
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* @note The default value is calculated for 48 MHz FLL output
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* from a 32.768 kHz external crystal.
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* (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
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*
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*/
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#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
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#define KINETIS_MCG_FLL_DRS 2
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#endif
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/**
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* @brief MCU system/core clock frequency.
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*/
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#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
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#define KINETIS_SYSCLK_FREQUENCY 48000000UL
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#endif
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/**
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* @brief MCU bus/flash clock frequency.
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*/
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#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
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#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_MCG_FLL_OUTDIV4)
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#endif
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/**
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* @brief UART0 clock frequency.
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* @note The default value is based on 96 MHz PLL/2 source.
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* If you use a different source, such as the FLL,
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* you must set this properly.
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*/
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#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
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#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
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#endif
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/**
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* @brief UART0 clock source.
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* @note The default value is to use PLL/2 or FLL source.
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*/
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#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
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#define KINETIS_UART0_CLOCK_SRC 1
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !defined(KINETIS_SYSCLK_FREQUENCY)
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#error KINETIS_SYSCLK_FREQUENCY must be defined
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#endif
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#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
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#error KINETIS_SYSCLK_FREQUENCY out of range
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#endif
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#if !defined(KINETIS_BUSCLK_FREQUENCY)
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#error KINETIS_BUSCLK_FREQUENCY must be defined
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#endif
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#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
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#error KINETIS_BUSCLK_FREQUENCY out of range
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#endif
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#if !(defined(KINETIS_MCG_FLL_OUTDIV1) && \
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KINETIS_MCG_FLL_OUTDIV1 >= 1 && KINETIS_MCG_FLL_OUTDIV1 <= 16)
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#error KINETIS_MCG_FLL_OUTDIV1 must be 1 through 16
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#endif
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#if !(defined(KINETIS_MCG_FLL_OUTDIV4) && \
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KINETIS_MCG_FLL_OUTDIV4 >= 1 && KINETIS_MCG_FLL_OUTDIV4 <= 8)
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#error KINETIS_MCG_FLL_OUTDIV4 must be 1 through 8
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#endif
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#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
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#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
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#endif
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#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
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#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type representing a system clock frequency.
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*/
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typedef uint32_t halclock_t;
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/**
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* @brief Type of the realtime free counter value.
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*/
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typedef uint32_t halrtcnt_t;
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Returns the current value of the system free running counter.
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* @note This service is implemented by returning the content of the
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* DWT_CYCCNT register.
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*
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* @return The value of the system free running counter of
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* type halrtcnt_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_value() 0
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/**
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* @brief Realtime counter frequency.
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* @note The DWT_CYCCNT register is incremented directly by the system
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* clock so this function returns STM32_HCLK.
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*
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* @return The realtime counter frequency of type halclock_t.
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*
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* @notapi
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*/
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#define hal_lld_get_counter_frequency() 0
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#include "nvic.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void mk20d50_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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