143 lines
4.4 KiB
C
143 lines
4.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file templates/hal_lld.c
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* @brief HAL Driver subsystem low level driver source template.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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* @todo Use a macro to define the system clock frequency.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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}
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/**
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* @brief MK20D5 clock initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function is meant to be invoked early during the system
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* initialization, it is usually invoked from the file
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* @p board.c.
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* @todo This function needs to be more generic.
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*
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* @special
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*/
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void mk20d50_clock_init(void) {
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/* Disable the watchdog */
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WDOG->UNLOCK = 0xC520;
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WDOG->UNLOCK = 0xD928;
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WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
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SIM->SCGC5 |= SIM_SCGC5_PORTA |
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SIM_SCGC5_PORTB |
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SIM_SCGC5_PORTC |
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SIM_SCGC5_PORTD |
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SIM_SCGC5_PORTE;
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/* EXTAL0 and XTAL0 */
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PORTA->PCR[18] = 0;
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PORTA->PCR[19] = 0;
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/*
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* Start in FEI mode
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*/
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/* Disable capacitors for crystal */
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OSC->CR = 0;
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/* Enable OSC, 8-32 MHz range, low power mode */
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MCG->C2 = MCG_C2_RANGE0(1) | MCG_C2_LOCRE0 | MCG_C2_EREFS0;
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/* Switch to crystal as clock source, FLL input of 8 MHz / 256 = 31.25 KHz */
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MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
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/* Wait for crystal oscillator to begin */
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while (!(MCG->S & MCG_S_OSCINIT0));
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/* Wait for the FLL to use the oscillator */
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while (MCG->S & MCG_S_IREFST);
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/* Wait for the MCGOUTCLK to use the oscillator */
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while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
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/*
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* Now in FBE mode
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*/
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/* Config PLL input for 2 MHz (8 MHz crystal / 4) */
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MCG->C5 = MCG_C5_PRDIV0(3);
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/* Config PLL for 96 MHz output */
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MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
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/* Wait for PLL to start using crystal as its input */
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while (!(MCG->S & MCG_S_PLLST));
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/* Wait for PLL to lock */
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while (!(MCG->S & MCG_S_LOCK0));
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/*
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* Now in PBE mode
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*/
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/* Switch to PLL as clock source */
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MCG->C1 = MCG_C1_CLKS(0);
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/* Wait for PLL clock to be used */
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while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
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/*
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* Now in PEE mode
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*/
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}
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/** @} */
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