281 lines
11 KiB
C
281 lines
11 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file stm32_dma.h
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* @brief STM32 DMA helper driver header.
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* @note This file requires definitions from the ST STM32 header file
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* stm3232f10x.h.
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*
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* @addtogroup STM32_DMA
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* @{
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*/
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#ifndef _STM32_DMA_H_
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#define _STM32_DMA_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/** @brief DMA1 identifier.*/
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#define STM32_DMA1_ID 0
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/** @brief DMA2 identifier.*/
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#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
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#define STM32_DMA2_ID 1
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#endif
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief STM32 DMA channel memory structure type.
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*/
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typedef struct {
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volatile uint32_t CCR;
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volatile uint32_t CNDTR;
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volatile uint32_t CPAR;
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volatile uint32_t CMAR;
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volatile uint32_t dummy;
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} stm32_dma_channel_t;
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/**
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* @brief STM32 DMA subsystem memory structure type.
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* @note This structure has been redefined here because it is convenient to
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* have the channels organized as an array, the ST header does not
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* do that.
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*/
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typedef struct {
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volatile uint32_t ISR;
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volatile uint32_t IFCR;
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stm32_dma_channel_t channels[7];
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} stm32_dma_t;
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/**
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* @brief STM32 DMA ISR function type.
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*
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* @param[in] p parameter for the registered function
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* @param[in] flags pre-shifted content of the ISR register
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*/
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typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/** DMA1 registers block numeric address.*/
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#define STM32_DMA1_BASE (AHBPERIPH_BASE + 0x0000)
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/** Pointer to the DMA1 registers block.*/
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#define STM32_DMA1 ((stm32_dma_t *)STM32_DMA1_BASE)
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/** Pointer to the DMA1 channel 1 registers block.*/
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#define STM32_DMA1_CH1 (&STM32_DMA1->channels[0])
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/** Pointer to the DMA1 channel 2 registers block.*/
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#define STM32_DMA1_CH2 (&STM32_DMA1->channels[1])
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/** Pointer to the DMA1 channel 3 registers block.*/
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#define STM32_DMA1_CH3 (&STM32_DMA1->channels[2])
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/** Pointer to the DMA1 channel 4 registers block.*/
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#define STM32_DMA1_CH4 (&STM32_DMA1->channels[3])
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/** Pointer to the DMA1 channel 5 registers block.*/
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#define STM32_DMA1_CH5 (&STM32_DMA1->channels[4])
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/** Pointer to the DMA1 channel 6 registers block.*/
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#define STM32_DMA1_CH6 (&STM32_DMA1->channels[5])
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/** Pointer to the DMA1 channel 7 registers block.*/
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#define STM32_DMA1_CH7 (&STM32_DMA1->channels[6])
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#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
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/** DMA2 registers block numeric address.*/
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#define STM32_DMA2_BASE (AHBPERIPH_BASE + 0x0400)
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/** Pointer to the DMA2 registers block.*/
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#define STM32_DMA2 ((stm32_dma_t *)STM32_DMA2_BASE)
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/** Pointer to the DMA2 channel 1 registers block.*/
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#define STM32_DMA2_CH1 (&STM32_DMA2->channels[0])
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/** Pointer to the DMA2 channel 2 registers block.*/
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#define STM32_DMA2_CH2 (&STM32_DMA2->channels[1])
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/** Pointer to the DMA2 channel 3 registers block.*/
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#define STM32_DMA2_CH3 (&STM32_DMA2->channels[2])
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/** Pointer to the DMA2 channel 4 registers block.*/
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#define STM32_DMA2_CH4 (&STM32_DMA2->channels[3])
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/** Pointer to the DMA2 channel 5 registers block.*/
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#define STM32_DMA2_CH5 (&STM32_DMA2->channels[4])
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#endif
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#define STM32_DMA_CHANNEL_1 0 /**< @brief DMA channel 1. */
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#define STM32_DMA_CHANNEL_2 1 /**< @brief DMA channel 2. */
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#define STM32_DMA_CHANNEL_3 2 /**< @brief DMA channel 3. */
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#define STM32_DMA_CHANNEL_4 3 /**< @brief DMA channel 4. */
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#define STM32_DMA_CHANNEL_5 4 /**< @brief DMA channel 5. */
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#define STM32_DMA_CHANNEL_6 5 /**< @brief DMA channel 6. */
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#define STM32_DMA_CHANNEL_7 6 /**< @brief DMA channel 7. */
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/**
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* @brief Associates a peripheral data register to a DMA channel.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmachp dmachp to a stm32_dma_channel_t structure
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* @param[in] cpar value to be written in the CPAR register
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*
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* @special
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*/
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#define dmaChannelSetPeripheral(dmachp, cpar) { \
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(dmachp)->CPAR = (uint32_t)(cpar); \
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}
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/**
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* @brief DMA channel setup by channel pointer.
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* @note This macro does not change the CPAR register because that register
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* value does not change frequently, it usually points to a peripheral
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* data register.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmachp dmachp to a stm32_dma_channel_t structure
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* @param[in] cndtr value to be written in the CNDTR register
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* @param[in] cmar value to be written in the CMAR register
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* @param[in] ccr value to be written in the CCR register
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*
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* @special
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*/
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#define dmaChannelSetup(dmachp, cndtr, cmar, ccr) { \
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(dmachp)->CNDTR = (uint32_t)(cndtr); \
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(dmachp)->CMAR = (uint32_t)(cmar); \
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(dmachp)->CCR = (uint32_t)(ccr); \
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}
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/**
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* @brief DMA channel enable by channel pointer.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmachp dmachp to a stm32_dma_channel_t structure
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*
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* @special
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*/
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#define dmaChannelEnable(dmachp) { \
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(dmachp)->CCR |= DMA_CCR1_EN; \
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}
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/**
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* @brief DMA channel disable by channel pointer.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmachp dmachp to a stm32_dma_channel_t structure
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*
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* @special
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*/
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#define dmaChannelDisable(dmachp) { \
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(dmachp)->CCR = 0; \
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}
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/**
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* @brief DMA channel setup by channel ID.
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* @note This macro does not change the CPAR register because that register
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* value does not change frequently, it usually points to a peripheral
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* data register.
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* @note Channels are numbered from 0 to 6, use the appropriate macro
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* as parameter.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmap pointer to a stm32_dma_t structure
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* @param[in] ch channel number
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* @param[in] cndtr value to be written in the CNDTR register
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* @param[in] cmar value to be written in the CMAR register
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* @param[in] ccr value to be written in the CCR register
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*
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* @special
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*/
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#define dmaSetupChannel(dmap, ch, cndtr, cmar, ccr) { \
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dmaChannelSetup(&(dmap)->channels[ch], (cndtr), (cmar), (ccr)); \
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}
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/**
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* @brief DMA channel enable by channel ID.
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* @note Channels are numbered from 0 to 6, use the appropriate macro
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* as parameter.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmap pointer to a stm32_dma_t structure
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* @param[in] ch channel number
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*
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* @special
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*/
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#define dmaEnableChannel(dmap, ch) { \
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dmaChannelEnable(&(dmap)->channels[ch]); \
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}
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/**
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* @brief DMA channel disable by channel ID.
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* @note Channels are numbered from 0 to 6, use the appropriate macro
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* as parameter.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmap pointer to a stm32_dma_t structure
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* @param[in] ch channel number
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*
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* @special
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*/
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#define dmaDisableChannel(dmap, ch) { \
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dmaChannelDisable(&(dmap)->channels[ch]); \
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}
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/**
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* @brief DMA channel interrupt sources clear.
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* @details Sets the appropriate CGIF bit into the IFCR register in order to
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* withdraw all the pending interrupt bits from the ISR register.
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* @note Channels are numbered from 0 to 6, use the appropriate macro
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* as parameter.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmap pointer to a stm32_dma_t structure
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* @param[in] ch channel number
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*
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* @special
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*/
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#define dmaClearChannel(dmap, ch){ \
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(dmap)->IFCR = 1 << ((ch) * 4); \
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}
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dmaInit(void);
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void dmaAllocate(uint32_t dma, uint32_t channel,
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stm32_dmaisr_t func, void *param);
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void dmaRelease(uint32_t dma, uint32_t channel);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _STM32_DMA_H_ */
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/** @} */
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