195 lines
7.4 KiB
C
195 lines
7.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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LPC43xx HAL driver - Copyright (C) 2013 Marcin Jokel
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file LPC43xx/hal_lld.c
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* @brief LPC43xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/**
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* @brief Register missing in NXP header file.
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*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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#define LPC_IDIV_ARRAY_NUM 5
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#define LPC_BASE_CLK_ARRAY_NUM 27
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const uint32_t lpc_idiv[LPC_IDIV_ARRAY_NUM] = {
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(((uint32_t)LPC_IDIVA_SRC) << 24) | (LPC_IDIVA_DIV << 2) | (!LPC_IDIVA_ENABLE),
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(((uint32_t)LPC_IDIVB_SRC) << 24) | (LPC_IDIVB_DIV << 2) | (!LPC_IDIVB_ENABLE),
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(((uint32_t)LPC_IDIVC_SRC) << 24) | (LPC_IDIVC_DIV << 2) | (!LPC_IDIVC_ENABLE),
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(((uint32_t)LPC_IDIVD_SRC) << 24) | (LPC_IDIVD_DIV << 2) | (!LPC_IDIVD_ENABLE),
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(((uint32_t)LPC_IDIVE_SRC) << 24) | (LPC_IDIVE_DIV << 2) | (!LPC_IDIVE_ENABLE)
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};
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const uint32_t lpc_base_clk[LPC_BASE_CLK_ARRAY_NUM] = {
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(CLK_SEL_PLL0USB << 24) | (!LPC_BASE_USB0_CLK_ENABLE),
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(((uint32_t)LPC_BASE_PERIPH_CLK_SRC) << 24) | (!LPC_BASE_PERIPH_CLK_ENABLE),
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(((uint32_t)LPC_BASE_USB1_CLK_SRC) << 24) | (!LPC_BASE_USB1_CLK_ENABLE),
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(((uint32_t)LPC_BASE_M4_CLK_SRC) << 24) | (!LPC_BASE_M4_CLK_ENABLE),
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(((uint32_t)LPC_BASE_SPIFI_CLK_SRC) << 24) | (!LPC_BASE_SPIFI_CLK_ENABLE),
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(((uint32_t)LPC_BASE_SPI_CLK_SRC) << 24) | (!LPC_BASE_SPI_CLK_ENABLE),
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(((uint32_t)LPC_BASE_PHY_RX_CLK_SRC) << 24) | (!LPC_BASE_PHY_RX_CLK_ENABLE),
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(((uint32_t)LPC_BASE_PHY_TX_CLK_SRC) << 24) | (!LPC_BASE_PHY_TX_CLK_ENABLE),
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(((uint32_t)LPC_BASE_APB1_CLK_SRC) << 24) | (!LPC_BASE_APB1_CLK_ENABLE),
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(((uint32_t)LPC_BASE_APB3_CLK_SRC) << 24) | (!LPC_BASE_APB3_CLK_ENABLE),
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(((uint32_t)LPC_BASE_LCD_CLK_SRC) << 24) | (!LPC_BASE_LCD_CLK_ENABLE),
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0,
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(((uint32_t)LPC_BASE_SDIO_CLK_SRC) << 24) | (!LPC_BASE_SDIO_CLK_ENABLE),
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(((uint32_t)LPC_BASE_SSP0_CLK_SRC) << 24) | (!LPC_BASE_SSP0_CLK_ENABLE),
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(((uint32_t)LPC_BASE_SSP1_CLK_SRC) << 24) | (!LPC_BASE_SSP1_CLK_ENABLE),
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(((uint32_t)LPC_BASE_UART0_CLK_SRC) << 24) | (!LPC_BASE_UART0_CLK_ENABLE),
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(((uint32_t)LPC_BASE_UART1_CLK_SRC) << 24) | (!LPC_BASE_UART1_CLK_ENABLE),
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(((uint32_t)LPC_BASE_UART2_CLK_SRC) << 24) | (!LPC_BASE_UART2_CLK_ENABLE),
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(((uint32_t)LPC_BASE_UART3_CLK_SRC) << 24) | (!LPC_BASE_UART3_CLK_ENABLE),
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(((uint32_t)LPC_BASE_OUT_CLK_SRC) << 24) | (!LPC_BASE_OUT_CLK_ENABLE),
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0,
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0,
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0,
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0,
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(((uint32_t)LPC_BASE_APLL_CLK_SRC) << 24) | (!LPC_BASE_APLL_CLK_ENABLE),
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(((uint32_t)LPC_BASE_CGU_OUT0_CLK_SRC) << 24) | (!LPC_BASE_CGU_OUT0_CLK_ENABLE),
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(((uint32_t)LPC_BASE_CGU_OUT1_CLK_SRC) << 24) | (!LPC_BASE_CGU_OUT1_CLK_ENABLE)
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* SysTick initialization using the system clock.*/
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nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
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SysTick->LOAD = LPC_BASE_M4_CLK / CH_FREQUENCY - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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/* DWT cycle counter enable.*/
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SCS_DEMCR |= SCS_DEMCR_TRCENA;
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DWT_CTRL |= DWT_CTRL_CYCCNTENA;
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#if defined(LPC_DMA_REQUIRED)
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dmaInit();
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#endif
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}
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/**
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* @brief LPC43xx clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function must be invoked only after the system reset.
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*
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* @special
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*/
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void lpc_clock_init(void) {
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uint32_t i;
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volatile uint32_t * preg;
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#if !LPC_FLASHLESS
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/* Flash wait states setting.*/
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preg = (volatile uint32_t *) 0x40043120; /* FLASHCFGA */
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*preg = (1UL<< 31) | (LPC_FLASHCFG_FLASHTIM << 12) | 0x3A;
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*(preg + 1)= (1UL<< 31) | (LPC_FLASHCFG_FLASHTIM << 12) | 0x3A; /* FLASHCFGB 0x40043124 */
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#endif
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/* System oscillator initialization if required.*/
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#if LPC_XTAL_ENABLE
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LPC_CGU->XTAL_OSC_CTRL = (LPC_OSCRANGE << 2); /* Enable Main oscillator */
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for(i = 0; i < 1000000; i++)
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; /* Wait for main oscillator to be ready */
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LPC_CGU->BASE_M4_CLK = (CLK_SEL_XTAL << 24); /* Select the crystal oscillator */
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/* as clock source for BASE_M4_CLK */
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#else
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LPC_CGU->BASE_M4_CLK = (CLK_SEL_IRC << 24); /* Select IRC as clock source for BASE_M4_CLK */
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#endif
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LPC_CGU->PLL1_CTRL = 0; /* Power-down PLL1 enabled by Boot ROM */
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#if LPC_PLL1_ENABLE /* PLL1 works in direct or non-integer mode. */
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/* Set PLL1 to FCLKOUT/2 */
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LPC_CGU->PLL1_CTRL = (1UL << 24) | (LPC_PLL1_CTRL_MSEL << 16) |
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(LPC_PLL1_CTRL_NSEL << 12);
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while (!(LPC_CGU->PLL1_STAT & 0x01))
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; /* Wait for PLL1 locked */
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LPC_CGU->BASE_M4_CLK = (CLK_SEL_PLL1 << 24); /* Select PPL1 clock as source for BASE_M4_CLK. */
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for(i = 0; i < 200000; i++)
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; /* Wait */
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#if LPC_PLL1_POSTDIV_ENABLE
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LPC_CGU->PLL1_CTRL |= (LPC_PLL1_CTRL_PSEL << 8);
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#else
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LPC_CGU->PLL1_CTRL |= (1UL << 7); /* Set PLL1 to FCLKOUT > 156 MHz*/
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#endif
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#endif /* LPC_PLL1_ENABLE == TRUE */
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/* Config integer dividers. */
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preg = &LPC_CGU->IDIVA_CTRL;
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for (i = 0; i < LPC_IDIV_ARRAY_NUM; i++) {
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*preg = lpc_idiv[i];
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preg++;
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}
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/* Config base clocks. */
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preg = &LPC_CGU->BASE_USB0_CLK;
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for (i = 0; i < LPC_BASE_CLK_ARRAY_NUM; i++) {
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*preg = lpc_base_clk[i];
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preg++;
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}
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#if LPC_PLL0USB0_ENABLE
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#error "PPL0USB0 not supported."
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#endif /* LPC_PLL0USB_ENABLE == TRUE */
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#if LPC_PLL0AUDIO_ENABLE
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#error "PLL0AUDIO not supported."
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#endif /* LPC_PLL0AUDIO == TRUE */
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}
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/** @} */
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