181 lines
6.0 KiB
C
181 lines
6.0 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32L1xx/hal_lld.c
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* @brief STM32L1xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*
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* @notapi
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals.*/
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rccResetAHB(!RCC_AHBRSTR_FLITFRST);
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rccResetAPB1(!RCC_APB1RSTR_PWRRST);
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rccResetAPB2(!0);
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/* SysTick initialization using the system clock.*/
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SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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}
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/**
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* @brief STM32L1xx voltage, clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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#if defined(STM32L1XX_MD) || defined(__DOXYGEN__)
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/**
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* @brief Clocks and internal voltage initialization.
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* PWR clock enable.*/
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RCC->APB1ENR = RCC_APB1ENR_PWREN;
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/* Core voltage setup.*/
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while ((PWR->CSR & PWR_CSR_VOSF) != 0)
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; /* Waits until regulator is stable. */
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PWR->CR = STM32_VOS;
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while ((PWR->CSR & PWR_CSR_VOSF) != 0)
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; /* Waits until regulator is stable. */
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/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
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always enabled because it is the fallback clock when PLL the fails.
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Trim fields are not altered from reset values.*/
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RCC->CFGR = 0;
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RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
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RCC->CSR = RCC_CSR_RMVF;
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RCC->CR = RCC_CR_MSION;
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while ((RCC->CR & RCC_CR_MSIRDY) == 0)
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; /* Waits until MSI is stable. */
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#if STM32_HSI_ENABLED
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/* HSI activation.*/
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Waits until HSI is stable. */
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#endif
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0)
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; /* Waits until HSE is stable. */
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#endif
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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; /* Waits until LSI is stable. */
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#endif
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#if STM32_LSE_ENABLED
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/* LSE activation, have to unlock the register.*/
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if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
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PWR->CR |= PWR_CR_DBP;
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RCC->CSR |= RCC_CSR_LSEON;
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PWR->CR &= ~PWR_CR_DBP;
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}
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while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
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; /* Waits until LSE is stable. */
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CR |= STM32_RTCPRE;
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RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
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STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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RCC->CSR |= STM32_RTCSEL;
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/* Flash setup and final clock selection. */
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#if defined(STM32_FLASHBITS1)
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FLASH->ACR = STM32_FLASHBITS1;
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#endif
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#if defined(STM32_FLASHBITS2)
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FLASH->ACR = STM32_FLASHBITS2;
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#endif
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/* Switching to the configured clock source if it is different from MSI.*/
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#if (STM32_SW != STM32_SW_MSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#endif
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#endif /* STM32_NO_INIT */
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
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}
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#else
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void stm32_clock_init(void) {}
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#endif
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/** @} */
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