112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include <pal.h>
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#include <nvic.h>
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#include "board.h"
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#include "stm32_serial.h"
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/*
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* Digital I/O ports static configuration as defined in @p board.h.
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*/
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static const STM32GPIOConfig config =
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{
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
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{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
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{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
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{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}
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};
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/*
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* Early initialization code.
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* This initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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void hwinit0(void) {
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/*
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* Clocks and PLL initialization.
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*/
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// HSI setup.
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RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; // Waits until HSI stable, it should already be.
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// HSE setup.
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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; // Waits until HSE stable.
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// PLL setup.
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RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; // Waits until PLL stable.
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// Clock sources.
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 |
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RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 |
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RCC_CFGR_MCO_NOCLOCK | USBPREBITS;
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/*
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* Flash setup and final clock selection.
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*/
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FLASH->ACR = FLASHBITS; // Flash wait states depending on clock.
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RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock.
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while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)
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;
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/*
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* I/O ports initialization as specified in board.h.
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*/
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palInit(&config);
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}
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/*
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* Late initialization code.
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* This initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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void hwinit1(void) {
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/*
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* NVIC/SCB initialization.
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*/
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SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0x3); // PRIGROUP 4:0 (4:4).
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NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
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NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
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NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
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/*
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* SysTick initialization.
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*/
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ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
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ST_CVR = 0;
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ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS;
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/*
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* Other subsystems initialization.
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*/
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serial_init(0xC0, 0xC0, 0xC0);
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/*
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* ChibiOS/RT initialization.
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*/
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chSysInit();
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}
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