1883 lines
75 KiB
C
1883 lines
75 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F3xx/stm32_registry.h
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* @brief STM32F3xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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/**
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* @brief Sub-family identifier.
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*/
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#if !defined(STM32F3XX) || defined(__DOXYGEN__)
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#define STM32F3XX
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F3xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* STM32F303xC. */
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/*===========================================================================*/
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#if defined(STM32F303xC) || defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 TRUE
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#define STM32_HAS_ADC4 TRUE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 14
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA1_CH1_HANDLER Vector6C
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#define STM32_DMA1_CH2_HANDLER Vector70
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#define STM32_DMA1_CH3_HANDLER Vector74
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#define STM32_DMA1_CH4_HANDLER Vector78
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#define STM32_DMA1_CH5_HANDLER Vector7C
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#define STM32_DMA1_CH6_HANDLER Vector80
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#define STM32_DMA1_CH7_HANDLER Vector84
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#define STM32_DMA1_CH1_NUMBER 11
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#define STM32_DMA1_CH2_NUMBER 12
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#define STM32_DMA1_CH3_NUMBER 13
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#define STM32_DMA1_CH4_NUMBER 14
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#define STM32_DMA1_CH5_NUMBER 15
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH7_NUMBER 17
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#define STM32_DMA2_NUM_CHANNELS 5
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#define STM32_DMA2_CH1_HANDLER Vector120
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#define STM32_DMA2_CH2_HANDLER Vector124
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#define STM32_DMA2_CH3_HANDLER Vector128
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#define STM32_DMA2_CH4_HANDLER Vector12C
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#define STM32_DMA2_CH5_HANDLER Vector130
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#define STM32_DMA2_CH1_NUMBER 56
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#define STM32_DMA2_CH2_NUMBER 57
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#define STM32_DMA2_CH3_NUMBER 58
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#define STM32_DMA2_CH4_NUMBER 59
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#define STM32_DMA2_CH5_NUMBER 60
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 34
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#define STM32_EXTI_IMR_MASK 0x1F800000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | \
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RCC_AHBENR_GPIOFEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 1
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
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#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_USART2 TRUE
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_HAS_USART3 TRUE
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
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#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB TRUE
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#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
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#define STM32_USB_PMA_SIZE 512
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#define STM32_USB_HAS_BCDR FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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#endif /* defined(STM32F303xC) */
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/*===========================================================================*/
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/* STM32F303x8. */
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/*===========================================================================*/
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#if defined(STM32F303x8)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 14
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_DAC2_CH1 TRUE
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#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA1_CH1_HANDLER Vector6C
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#define STM32_DMA1_CH2_HANDLER Vector70
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#define STM32_DMA1_CH3_HANDLER Vector74
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#define STM32_DMA1_CH4_HANDLER Vector78
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#define STM32_DMA1_CH5_HANDLER Vector7C
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#define STM32_DMA1_CH6_HANDLER Vector80
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#define STM32_DMA1_CH7_HANDLER Vector84
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#define STM32_DMA1_CH1_NUMBER 11
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#define STM32_DMA1_CH2_NUMBER 12
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#define STM32_DMA1_CH3_NUMBER 13
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#define STM32_DMA1_CH4_NUMBER 14
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#define STM32_DMA1_CH5_NUMBER 15
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH7_NUMBER 17
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#define STM32_DMA2_NUM_CHANNELS 0
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_LINES 34
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#define STM32_EXTI_IMR_MASK 0x1F800000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_I2C3 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_USART2 TRUE
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_HAS_USART3 TRUE
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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#endif /* defined(STM32F303x8) */
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/*===========================================================================*/
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|
/* STM32F301x8. */
|
|
/*===========================================================================*/
|
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#if defined(STM32F301x8)
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|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
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#define STM32_HAS_ADC2 FALSE
|
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#define STM32_HAS_ADC3 FALSE
|
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#define STM32_HAS_ADC4 FALSE
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|
|
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#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
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|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 FALSE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
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|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
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#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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|
|
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#define STM32_HAS_DAC1_CH2 FALSE
|
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#define STM32_HAS_DAC2_CH1 FALSE
|
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#define STM32_HAS_DAC2_CH2 FALSE
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|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
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#define STM32_DMA_SUPPORTS_CSELR FALSE
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|
|
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#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
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#define STM32_DMA1_CH5_HANDLER Vector7C
|
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#define STM32_DMA1_CH6_HANDLER Vector80
|
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#define STM32_DMA1_CH7_HANDLER Vector84
|
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#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
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#define STM32_DMA1_CH5_NUMBER 15
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#define STM32_DMA1_CH6_NUMBER 16
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#define STM32_DMA1_CH7_NUMBER 17
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|
|
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#define STM32_DMA2_NUM_CHANNELS 0
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|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
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|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 33
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
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|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
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#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
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#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
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RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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|
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#define STM32_HAS_I2C2 TRUE
|
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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|
|
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#define STM32_HAS_I2C3 TRUE
|
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#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
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#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
|
|
|
#define STM32_HAS_I2C4 FALSE
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|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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|
|
#define STM32_HAS_SPI1 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
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|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
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|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
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|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
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|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
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|
|
|
#define STM32_HAS_TIM3 FALSE
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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|
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
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|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
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|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
#endif /* defined(STM32F301x8) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F302x8. */
|
|
/*===========================================================================*/
|
|
#if defined(STM32F302x8)
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
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|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
|
#define STM32_DMA1_CH5_HANDLER Vector7C
|
|
#define STM32_DMA1_CH6_HANDLER Vector80
|
|
#define STM32_DMA1_CH7_HANDLER Vector84
|
|
#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
|
#define STM32_DMA1_CH5_NUMBER 15
|
|
#define STM32_DMA1_CH6_NUMBER 16
|
|
#define STM32_DMA1_CH7_NUMBER 17
|
|
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 33
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_SPI1 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM3 FALSE
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
|
|
#define STM32_USB_PMA_SIZE 768
|
|
#define STM32_USB_HAS_BCDR FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
#endif /* defined(STM32F302x8) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F302xC. */
|
|
/*===========================================================================*/
|
|
#if defined(STM32F302xC)
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
|
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
|
#define STM32_DMA1_CH5_HANDLER Vector7C
|
|
#define STM32_DMA1_CH6_HANDLER Vector80
|
|
#define STM32_DMA1_CH7_HANDLER Vector84
|
|
#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
|
#define STM32_DMA1_CH5_NUMBER 15
|
|
#define STM32_DMA1_CH6_NUMBER 16
|
|
#define STM32_DMA1_CH7_NUMBER 17
|
|
|
|
#define STM32_DMA2_NUM_CHANNELS 5
|
|
#define STM32_DMA2_CH1_HANDLER Vector120
|
|
#define STM32_DMA2_CH2_HANDLER Vector124
|
|
#define STM32_DMA2_CH3_HANDLER Vector128
|
|
#define STM32_DMA2_CH4_HANDLER Vector12C
|
|
#define STM32_DMA2_CH5_HANDLER Vector130
|
|
#define STM32_DMA2_CH1_NUMBER 56
|
|
#define STM32_DMA2_CH2_NUMBER 57
|
|
#define STM32_DMA2_CH3_NUMBER 58
|
|
#define STM32_DMA2_CH4_NUMBER 59
|
|
#define STM32_DMA2_CH5_NUMBER 60
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 34
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOEEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
|
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
|
|
#define STM32_HAS_USART6 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
|
|
#define STM32_USB_PMA_SIZE 512
|
|
#define STM32_USB_HAS_BCDR FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
#endif /* defined(STM32F302xC) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F318x8. */
|
|
/*===========================================================================*/
|
|
#if defined(STM32F318x8)
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_HAS_ADC2 FALSE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_DAC1_CH2 FALSE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
|
#define STM32_DMA1_CH5_HANDLER Vector7C
|
|
#define STM32_DMA1_CH6_HANDLER Vector80
|
|
#define STM32_DMA1_CH7_HANDLER Vector84
|
|
#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
|
#define STM32_DMA1_CH5_NUMBER 15
|
|
#define STM32_DMA1_CH6_NUMBER 16
|
|
#define STM32_DMA1_CH7_NUMBER 17
|
|
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 33
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD FALSE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
|
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_SPI1 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM3 FALSE
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
#endif /* defined(STM32F318x8) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F328x8. */
|
|
/*===========================================================================*/
|
|
#if defined(STM32F328x8)
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_DAC2_CH1 TRUE
|
|
#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
|
#define STM32_DMA1_CH5_HANDLER Vector7C
|
|
#define STM32_DMA1_CH6_HANDLER Vector80
|
|
#define STM32_DMA1_CH7_HANDLER Vector84
|
|
#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
|
#define STM32_DMA1_CH5_NUMBER 15
|
|
#define STM32_DMA1_CH6_NUMBER 16
|
|
#define STM32_DMA1_CH7_NUMBER 17
|
|
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 33
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
|
|
#define STM32_HAS_I2C2 FALSE
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_SPI2 FALSE
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
|
|
#define STM32_HAS_UART4 FALSE
|
|
#define STM32_HAS_UART5 FALSE
|
|
#define STM32_HAS_USART6 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
#endif /* defined(STM32F328x8) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F358xC. */
|
|
/*===========================================================================*/
|
|
#if defined(STM32F358xC) || defined(__DOXYGEN__)
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
|
|
|
#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
|
|
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
|
#define STM32_DMA1_CH5_HANDLER Vector7C
|
|
#define STM32_DMA1_CH6_HANDLER Vector80
|
|
#define STM32_DMA1_CH7_HANDLER Vector84
|
|
#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
|
#define STM32_DMA1_CH5_NUMBER 15
|
|
#define STM32_DMA1_CH6_NUMBER 16
|
|
#define STM32_DMA1_CH7_NUMBER 17
|
|
|
|
#define STM32_DMA2_NUM_CHANNELS 5
|
|
#define STM32_DMA2_CH1_HANDLER Vector120
|
|
#define STM32_DMA2_CH2_HANDLER Vector124
|
|
#define STM32_DMA2_CH3_HANDLER Vector128
|
|
#define STM32_DMA2_CH4_HANDLER Vector12C
|
|
#define STM32_DMA2_CH5_HANDLER Vector130
|
|
#define STM32_DMA2_CH1_NUMBER 56
|
|
#define STM32_DMA2_CH2_NUMBER 57
|
|
#define STM32_DMA2_CH3_NUMBER 58
|
|
#define STM32_DMA2_CH4_NUMBER 59
|
|
#define STM32_DMA2_CH5_NUMBER 60
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 34
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOEEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
|
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
|
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM7 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM12 FALSE
|
|
#define STM32_HAS_TIM13 FALSE
|
|
#define STM32_HAS_TIM14 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
|
|
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
|
|
|
#define STM32_HAS_UART5 TRUE
|
|
|
|
#define STM32_HAS_USART6 FALSE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_HAS_USB TRUE
|
|
#define STM32_USB_ACCESS_SCHEME_2x16 FALSE
|
|
#define STM32_USB_PMA_SIZE 512
|
|
#define STM32_USB_HAS_BCDR FALSE
|
|
#define STM32_HAS_OTG1 FALSE
|
|
#define STM32_HAS_OTG2 FALSE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC FALSE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D FALSE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC FALSE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
#endif /* defined(STM32F358xC) */
|
|
|
|
/*===========================================================================*/
|
|
/* STM32F334x8. */
|
|
/*===========================================================================*/
|
|
#if defined(STM32F334x8) || defined(__DOXYGEN__)
|
|
/* ADC attributes.*/
|
|
#define STM32_HAS_ADC1 TRUE
|
|
#define STM32_HAS_ADC2 TRUE
|
|
#define STM32_HAS_ADC3 FALSE
|
|
#define STM32_HAS_ADC4 FALSE
|
|
|
|
#define STM32_HAS_SDADC1 FALSE
|
|
#define STM32_HAS_SDADC2 FALSE
|
|
#define STM32_HAS_SDADC3 FALSE
|
|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_CAN1 TRUE
|
|
#define STM32_HAS_CAN2 FALSE
|
|
#define STM32_CAN_MAX_FILTERS 14
|
|
|
|
/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
|
#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
|
|
|
#define STM32_HAS_DAC2_CH1 TRUE
|
|
#define STM32_DAC_DAC2_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
|
|
|
#define STM32_HAS_DAC2_CH2 FALSE
|
|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA FALSE
|
|
#define STM32_DMA_SUPPORTS_CSELR FALSE
|
|
|
|
#define STM32_DMA1_NUM_CHANNELS 7
|
|
#define STM32_DMA1_CH1_HANDLER Vector6C
|
|
#define STM32_DMA1_CH2_HANDLER Vector70
|
|
#define STM32_DMA1_CH3_HANDLER Vector74
|
|
#define STM32_DMA1_CH4_HANDLER Vector78
|
|
#define STM32_DMA1_CH5_HANDLER Vector7C
|
|
#define STM32_DMA1_CH6_HANDLER Vector80
|
|
#define STM32_DMA1_CH7_HANDLER Vector84
|
|
#define STM32_DMA1_CH1_NUMBER 11
|
|
#define STM32_DMA1_CH2_NUMBER 12
|
|
#define STM32_DMA1_CH3_NUMBER 13
|
|
#define STM32_DMA1_CH4_NUMBER 14
|
|
#define STM32_DMA1_CH5_NUMBER 15
|
|
#define STM32_DMA1_CH6_NUMBER 16
|
|
#define STM32_DMA1_CH7_NUMBER 17
|
|
|
|
#define STM32_DMA2_NUM_CHANNELS 0
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH FALSE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_NUM_LINES 33
|
|
#define STM32_EXTI_IMR_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE FALSE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG FALSE
|
|
#define STM32_HAS_GPIOH FALSE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ FALSE
|
|
#define STM32_HAS_GPIOK FALSE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
|
RCC_AHBENR_GPIOBEN | \
|
|
RCC_AHBENR_GPIOCEN | \
|
|
RCC_AHBENR_GPIODEN | \
|
|
RCC_AHBENR_GPIOFEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
|
|
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
|
|
|
|
#define STM32_HAS_I2C2 FALSE
|
|
#define STM32_HAS_I2C3 FALSE
|
|
#define STM32_HAS_I2C4 FALSE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 1
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDIO attributes.*/
|
|
#define STM32_HAS_SDIO FALSE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
|
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
|
|
|
#define STM32_HAS_SPI2 FALSE
|
|
#define STM32_HAS_SPI3 FALSE
|
|
#define STM32_HAS_SPI4 FALSE
|
|
#define STM32_HAS_SPI5 FALSE
|
|
#define STM32_HAS_SPI6 FALSE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM4 FALSE
|
|
#define STM32_HAS_TIM5 FALSE
|
|
#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_USART2 TRUE
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_HAS_USART3 TRUE
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC FALSE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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#endif /* defined(STM32F334x8) */
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/** @} */
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#endif /* _STM32_REGISTRY_H_ */
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/** @} */
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