150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include "lpc214x.h"
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#include "vic.h"
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#include "lpc214x_serial.h"
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#include "lpc214x_ssp.h"
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#include "board.h"
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#include "mmcsd.h"
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#include "buzzer.h"
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/*
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* Non-vectored IRQs handling here.
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*/
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__attribute__((naked))
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static void IrqHandler(void) {
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chSysIRQEnterI();
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/* nothing */
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VICVectAddr = 0;
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chSysIRQExitI();
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}
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/*
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* Timer 0 IRQ handling here.
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*/
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__attribute__((naked))
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static void T0IrqHandler(void) {
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chSysIRQEnterI();
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T0IR = 1; /* Clear interrupt on match MR0. */
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chSysTimerHandlerI();
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VICVectAddr = 0;
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chSysIRQExitI();
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}
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/*
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* Early initialization code.
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* This initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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void hwinit0(void) {
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/*
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* All peripherals clock disabled by default in order to save power.
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*/
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PCONP = PCRTC | PCTIM0;
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/*
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* MAM setup.
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*/
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MAMTIM = 0x3; /* 3 cycles for flash accesses. */
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MAMCR = 0x2; /* MAM fully enabled. */
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/*
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* PLL setup for Fosc=12MHz and CCLK=48MHz.
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* P=2 M=3.
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*/
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PLL *pll = PLLBase;
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pll->PLL0_CFG = 0x23; /* P and M values. */
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pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */
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pll->PLL0_FEED = 0xAA;
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pll->PLL0_FEED = 0x55;
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while (!(pll->PLL0_STAT & 0x400))
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; /* Wait for PLL lock. */
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pll->PLL0_CON = 0x3; /* Connects the PLL. */
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pll->PLL0_FEED = 0xAA;
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pll->PLL0_FEED = 0x55;
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/*
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* VPB setup.
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* PCLK = CCLK / 4.
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*/
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VPBDIV = VPD_D4;
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/*
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* I/O pins configuration.
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*/
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PINSEL0 = VAL_PINSEL0;
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PINSEL1 = VAL_PINSEL1;
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PINSEL2 = VAL_PINSEL2;
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IO0DIR = VAL_FIO0DIR;
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IO0SET = 0xFFFFFFFF;
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IO1DIR = VAL_FIO1DIR;
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IO1SET = 0xFFFFFFFF;
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}
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/*
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* Late initialization code.
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* This initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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void hwinit1(void) {
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/*
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* Interrupt vectors assignment.
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*/
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InitVIC();
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VICDefVectAddr = (IOREG32)IrqHandler;
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/*
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* System Timer initialization, 1ms intervals.
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*/
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SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
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VICIntEnable = INTMASK(SOURCE_Timer0);
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TC *timer = T0Base;
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timer->TC_PR = VAL_TC0_PRESCALER;
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timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1);
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timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */
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timer->TC_TCR = 2; /* Reset counter and prescaler. */
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timer->TC_TCR = 1; /* Timer enabled. */
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/*
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* Other subsystems.
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*/
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InitSerial(1, 2);
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InitSSP();
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InitMMC();
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InitBuzzer();
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/*
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* ChibiOS/RT initialization.
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*/
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chSysInit();
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}
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