313 lines
11 KiB
C
313 lines
11 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/i2c_lld.h
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* @brief STM32 I2C subsystem low level driver header.
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* @addtogroup I2C
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* @{
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*/
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#ifndef _I2C_LLD_H_
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#define _I2C_LLD_H_
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Switch between callback based and synchronouse driver.
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* @note The default is synchronouse.
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*/
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#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__)
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#define I2C_SUPPORTS_CALLBACKS TRUE
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#endif
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/**
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* @brief I2C1 driver synchronization choice between GPT and polling.
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* @note The default is polling wait.
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*/
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#if !defined(STM32_I2C_I2C1_USE_GPT_TIM) || \
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!defined(STM32_I2C_I2C1_USE_POLLING_WAIT) || \
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defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE
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#endif
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/**
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* @brief I2C2 driver synchronization choice between GPT and polling.
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* @note The default is polling wait.
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*/
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#if !defined(STM32_I2C_I2C2_USE_GPT_TIM) || \
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!defined(STM32_I2C_I2C2_USE_POLLING_WAIT) || \
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defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE
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#endif
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/**
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* @brief I2C1 driver enable switch.
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* @details If set to @p TRUE the support for I2C1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C1 TRUE
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#endif
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/**
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* @brief I2C2 driver enable switch.
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* @details If set to @p TRUE the support for I2C2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C2 TRUE
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#endif
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/**
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* @brief I2C1 interrupt priority level setting.
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* @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
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*/
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#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 0xA0
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#endif
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/**
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* @brief I2C2 interrupt priority level setting.
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* @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
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*/
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#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/** @brief EV5 */
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#define I2C_EV5_MASTER_MODE_SELECT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_SB)) /* BUSY, MSL and SB flag */
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/** @brief EV6 */
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#define I2C_EV6_MASTER_TRA_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_ADDR|I2C_SR1_TXE)) /* BUSY, MSL, ADDR, TXE and TRA flags */
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#define I2C_EV6_MASTER_REC_MODE_SELECTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADDR)) /* BUSY, MSL and ADDR flags */
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/** @brief EV7 */
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#define I2C_EV7_MASTER_REC_BYTE_RECEIVED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_RXNE)) /* BUSY, MSL and RXNE flags */
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#define I2C_EV7_MASTER_REC_BYTE_QUEUED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_BTF|I2C_SR1_RXNE)) /* BUSY, MSL, RXNE and BTF flags*/
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/** @brief EV8 */
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#define I2C_EV8_MASTER_BYTE_TRANSMITTING ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE flags */
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/** @brief EV8_2 */
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#define I2C_EV8_2_MASTER_BYTE_TRANSMITTED ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY|I2C_SR2_TRA)<< 16)|I2C_SR1_BTF|I2C_SR1_TXE)) /* TRA, BUSY, MSL, TXE and BTF flags */
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/** @brief EV9 */
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#define I2C_EV9_MASTER_ADDR_10BIT ((uint32_t)(((I2C_SR2_MSL|I2C_SR2_BUSY)<< 16)|I2C_SR1_ADD10)) /* BUSY, MSL and ADD10 flags */
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#define I2C_EV_MASK 0x00FFFFFF /* First byte zeroed because there is no need of PEC register part from SR2 */
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#define I2C_FLG_1BTR 0x01 /* Single byte to be received and processed */
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#define I2C_FLG_2BTR 0x02 /* Two bytes to be received and processed */
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#define I2C_FLG_3BTR 0x04 /* Last three received bytes to be processed */
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#define I2C_FLG_MASTER_RECEIVER 0x10
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#define I2C_FLG_HEADER_SENT 0x80
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#define I2C_FLG_TIMER_ARMED 0x40 /* Used to check locks on the bus */
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#define EV6_SUBEV_MASK (I2C_FLG_1BTR|I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
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#define EV7_SUBEV_MASK (I2C_FLG_2BTR|I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
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#define I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
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#define I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED (I2C_FLG_1BTR|I2C_FLG_MASTER_RECEIVER)
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#define I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS (I2C_FLG_3BTR|I2C_FLG_MASTER_RECEIVER)
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#define I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS (I2C_FLG_2BTR|I2C_FLG_MASTER_RECEIVER)
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief I2C Driver condition flags type.
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*/
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typedef uint32_t i2cflags_t;
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typedef enum {
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OPMODE_I2C = 1,
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OPMODE_SMBUS_DEVICE = 2,
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OPMODE_SMBUS_HOST = 3,
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} i2copmode_t;
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typedef enum {
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STD_DUTY_CYCLE = 1,
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FAST_DUTY_CYCLE_2 = 2,
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FAST_DUTY_CYCLE_16_9 = 3,
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} i2cdutycycle_t;
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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i2copmode_t op_mode; /**< @brief Specifies the I2C mode.*/
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uint32_t clock_speed; /**< @brief Specifies the clock frequency. Must be set to a value lower than 400kHz */
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i2cdutycycle_t duty_cycle; /**< @brief Specifies the I2C fast mode duty cycle */
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uint8_t own_addr_7; /**< @brief Specifies the first device 7-bit own address. */
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uint16_t own_addr_10; /**< @brief Specifies the second part of device own address in 10-bit mode. Set to NULL if not used. */
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uint8_t nbit_own_addr; /**< @brief Specifies if 7-bit or 10-bit address is acknowledged */
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} I2CConfig;
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/**
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* @brief Type of a structure representing an I2C driver.
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*/
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typedef struct I2CDriver I2CDriver;
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/**
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* @brief Type of a structure representing an I2C slave config.
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*/
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typedef struct I2CSlaveConfig I2CSlaveConfig;
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/**
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* @brief Structure representing an I2C driver.
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*/
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struct I2CDriver{
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/**
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* @brief Driver state.
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*/
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i2cstate_t id_state;
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#if I2C_USE_WAIT
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/**
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* @brief Thread waiting for I/O completion.
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*/
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Thread *id_thread;
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#endif /* I2C_USE_WAIT */
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#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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#if CH_USE_MUTEXES || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the bus.
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*/
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Mutex id_mutex;
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#elif CH_USE_SEMAPHORES
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Semaphore id_semaphore;
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#endif
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#endif /* I2C_USE_MUTUAL_EXCLUSION */
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/**
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* @brief Current configuration data.
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*/
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const I2CConfig *id_config;
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/**
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* @brief Current slave configuration data.
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*/
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const I2CSlaveConfig *id_slave_config;
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__IO size_t txbytes; /*!< @brief Number of bytes to be transmitted. */
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__IO size_t rxbytes; /*!< @brief Number of bytes to be received. */
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uint8_t *rxbuf; /*!< @brief Pointer to receive buffer. */
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uint8_t *txbuf; /*!< @brief Pointer to transmit buffer.*/
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uint8_t *rxbuff_p; /*!< @brief Pointer to the current byte in slave rx buffer. */
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uint8_t *txbuff_p; /*!< @brief Pointer to the current byte in slave tx buffer. */
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__IO i2cflags_t errors; /*!< @brief Error flags.*/
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__IO i2cflags_t flags; /*!< @brief State flags.*/
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uint16_t slave_addr; /*!< @brief Current slave address. */
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uint8_t slave_addr1;/*!< @brief 7-bit address of the slave with r\w bit.*/
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uint8_t slave_addr2;/*!< @brief Uses in 10-bit address mode. */
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#if CH_USE_EVENTS
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EventSource sevent; /*!< @brief Status Change @p EventSource.*/
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#endif
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/*********** End of the mandatory fields. **********************************/
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/**
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* @brief Pointer to the I2Cx registers block.
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*/
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I2C_TypeDef *id_i2c;
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#if !(STM32_I2C_I2C1_USE_POLLING_WAIT)
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/* TODO: capability to switch this GPT fields off */
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/**
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* @brief Timer for waiting STOP condition on the bus.
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* @details This is workaround for STM32 buggy I2C cell.
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*/
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GPTDriver *timer;
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/**
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* @brief Config for workaround timer.
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*/
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const GPTConfig *timer_cfg;
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#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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#define i2c_lld_bus_is_busy(i2cp) \
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(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)
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/* Wait until BUSY flag is reset: a STOP has been generated on the bus
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* signaling the end of transmission. Normally this wait function
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* does not block thread, only if slave not response it does.
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*/
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#define i2c_lld_wait_bus_free(i2cp) { \
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uint32_t tmo = 0xfffff; \
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while((i2cp->id_i2c->SR2 & I2C_SR2_BUSY) && tmo--) \
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; \
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}
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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/** @cond never*/
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#if STM32_I2C_USE_I2C1
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extern I2CDriver I2CD1;
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#endif
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#if STM32_I2C_USE_I2C2
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extern I2CDriver I2CD2;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void i2c_lld_init(void);
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void i2c_lld_reset(I2CDriver *i2cp);
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void i2c_lld_set_clock(I2CDriver *i2cp);
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void i2c_lld_set_opmode(I2CDriver *i2cp);
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void i2c_lld_set_own_address(I2CDriver *i2cp);
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void i2c_lld_start(I2CDriver *i2cp);
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void i2c_lld_stop(I2CDriver *i2cp);
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void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr,
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uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes);
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void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr,
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uint8_t *rxbuf, size_t rxbytes);
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void i2c_lld_master_transceive(I2CDriver *i2cp);
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#ifdef __cplusplus
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}
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#endif
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/** @endcond*/
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#endif /* CH_HAL_USE_I2C */
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#endif /* _I2C_LLD_H_ */
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