1512 lines
52 KiB
C
1512 lines
52 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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LPC43xx HAL driver - Copyright (C) 2013 Marcin Jokel
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file LPC43xx/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "LPC43xx.h"
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#include "nvic.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "LPC43xx"
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#define IRCOSCCLK 12000000UL /**< High speed internal clock. */
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#define CLK_SEL_32KHZ 0x00000000
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#define CLK_SEL_IRC 0x00000001
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#define CLK_SEL_ENET_RX_CLK 0x00000002
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#define CLK_SEL_ENET_TX_CLK 0x00000003
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#define CLK_SEL_GP_CLKIN 0x00000004
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#define CLK_SEL_XTAL 0x00000006
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#define CLK_SEL_PLL0USB 0x00000007
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#define CLK_SEL_PLL0AUDIO 0x00000008
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#define CLK_SEL_PLL1 0x00000009
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#define CLK_SEL_IDIVA 0x0000000C
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#define CLK_SEL_IDIVB 0x0000000D
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#define CLK_SEL_IDIVC 0x0000000E
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#define CLK_SEL_IDIVD 0x0000000F
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#define CLK_SEL_IDIVE 0x00000010
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Crystal oscillator enable.
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*/
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#if !defined(LPC_XTAL_ENABLE) || defined(__DOXYGEN__)
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#define LPC_XTAL_ENABLE TRUE
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#endif
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/**
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* @brief PLL1 enable.
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*/
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#if !defined(LPC_PLL1_ENABLE) || defined(__DOXYGEN__)
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#define LPC_PLL1_ENABLE TRUE
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#endif
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/**
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* @brief PLL1 multiplier.
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* @note Final frequency must not exceed the CCO ratings.
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*/
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#if !defined(LPC_PLL1_MUL) || defined(__DOXYGEN__)
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#define LPC_PLL1_MUL 17
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#endif
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/**
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* @brief PLL1 pre-divider.
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* @note The value must be in the 1..4 range and the final frequency
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* must not exceed the CCO ratings.
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*/
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#if !defined(LPC_PLL1_PREDIV) || defined(__DOXYGEN__)
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#define LPC_PLL1_PREDIV 1
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#endif
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/**
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* @brief PLL1 post-divider enable.
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*/
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#if !defined(LPC_PLL1_POSTDIV_ENABLE) || defined(__DOXYGEN__)
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#define LPC_PLL1_POSTDIV_ENABLE FALSE
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#endif
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/**
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* @brief PLL1 post-divider.
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* @note The value must be 2, 4, 8 or 16.
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*/
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#if !defined(LPC_PLL1_POSTDIV) || defined(__DOXYGEN__)
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#define LPC_PLL1_POSTDIV 2
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#endif
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/**
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* @brief USB0 PLL0 enable.
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*/
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#if !defined(LPC_PLL0USB_ENABLE) || defined(__DOXYGEN__)
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#define LPC_PLL0USB_ENABLE FALSE
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#endif
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/**
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* @brief Audio PLL0 enable.
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*/
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#if !defined(LPC_PLL0AUDIO_ENABLE) || defined(__DOXYGEN__)
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#define LPC_PLL0AUDIO_ENABLE FALSE
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#endif
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/**
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* @brief IDIVA clock divider enable.
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*/
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#if !defined(LPC_IDIVA_ENABLE) || defined(__DOXYGEN__)
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#define LPC_IDIVA_ENABLE FALSE
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#endif
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/**
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* @brief IDIVA clock divider source.
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*/
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#if !defined(LPC_IDIVA_SRC) || defined(__DOXYGEN__)
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#define LPC_IDIVA_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief IDIVA clock divider.
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*/
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#if !defined(LPC_IDIVA_DIV) || defined(__DOXYGEN__)
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#define LPC_IDIVA_DIV 1
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#endif
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/**
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* @brief IDIVB clock divider enable.
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*/
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#if !defined(LPC_IDIVB_ENABLE) || defined(__DOXYGEN__)
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#define LPC_IDIVB_ENABLE FALSE
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#endif
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/**
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* @brief IDIVB clock divider source.
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*/
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#if !defined(LPC_IDIVB_SRC) || defined(__DOXYGEN__)
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#define LPC_IDIVB_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief IDIVB clock divider.
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*/
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#if !defined(LPC_IDIVB_DIV) || defined(__DOXYGEN__)
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#define LPC_IDIVB_DIV 1
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#endif
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/**
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* @brief IDIVC clock divider enable.
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*/
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#if !defined(LPC_IDIVC_ENABLE) || defined(__DOXYGEN__)
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#define LPC_IDIVC_ENABLE TRUE
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#endif
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/**
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* @brief IDIVC clock divider source.
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*/
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#if !defined(LPC_IDIVC_SRC) || defined(__DOXYGEN__)
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#define LPC_IDIVC_SRC CLK_SEL_PLL1
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#endif
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/**
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* @brief IDIVC clock divider.
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*/
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#if !defined(LPC_IDIVC_DIV) || defined(__DOXYGEN__)
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#define LPC_IDIVC_DIV 3
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#endif
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/**
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* @brief IDIVD clock divider enable.
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*/
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#if !defined(LPC_IDIVD_ENABLE) || defined(__DOXYGEN__)
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#define LPC_IDIVD_ENABLE FALSE
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#endif
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/**
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* @brief IDIVD clock divider source.
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*/
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#if !defined(LPC_IDIVD_SRC) || defined(__DOXYGEN__)
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#define LPC_IDIVD_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief IDIVD clock divider.
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*/
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#if !defined(LPC_IDIVD_DIV) || defined(__DOXYGEN__)
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#define LPC_IDIVD_DIV 1
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#endif
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/**
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* @brief IDIVE clock divider enable.
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*/
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#if !defined(LPC_IDIVE_ENABLE) || defined(__DOXYGEN__)
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#define LPC_IDIVE_ENABLE FALSE
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#endif
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/**
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* @brief IDIVE clock divider source.
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*/
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#if !defined(LPC_IDIVE_SRC) || defined(__DOXYGEN__)
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#define LPC_IDIVE_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief IDIVE clock divider.
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*/
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#if !defined(LPC_IDIVE_DIV) || defined(__DOXYGEN__)
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#define LPC_IDIVE_DIV 1
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#endif
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/**
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* @brief Base M4 clock enable.
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* @note Must be always enabled.
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*/
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#if !defined(LPC_BASE_M4_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_M4_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base USB0 clock enable.
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*/
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#if !defined(LPC_BASE_USB0_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_USB0_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base peripheral clock enable.
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* @note Base clock for Cortex-M0SUB subsystem, SGPIO.
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*/
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#if !defined(LPC_BASE_PERIPH_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_PERIPH_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base peripheral clock source.
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*/
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#if !defined(LPC_BASE_PERIPH_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_PERIPH_CLK_SRC CLK_SEL_PLL1
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#endif
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/**
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* @brief Base USB1 clock enable.
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*/
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#if !defined(LPC_BASE_USB1_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_USB1_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base USB1 clock source.
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*/
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#if !defined(LPC_BASE_USB1_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_USB1_CLK_SRC CLK_SEL_PLL1
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#endif
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/**
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* @brief Base SPIFI clock enable.
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*/
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#if !defined(LPC_BASE_SPIFI_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_SPIFI_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base SPIFI clock source.
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*/
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#if !defined(LPC_BASE_SPIFI_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_SPIFI_CLK_SRC CLK_SEL_PLL1
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#endif
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/**
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* @brief Base SPI clock enable.
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*/
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#if !defined(LPC_BASE_SPI_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_SPI_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base SPI clock source.
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*/
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#if !defined(LPC_BASE_SPI_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_SPI_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base Ethernet PHY Receive clock enable.
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*/
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#if !defined(LPC_BASE_PHY_RX_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_PHY_RX_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base Ethernet PHY Receive clock source.
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*/
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#if !defined(LPC_BASE_PHY_RX_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_PHY_RX_CLK_SRC CLK_SEL_IDIVC
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#endif
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/**
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* @brief Base Ethernet PHY Transmit clock enable.
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*/
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#if !defined(LPC_BASE_PHY_TX_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_PHY_TX_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base Ethernet PHY Transmit clock source.
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*/
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#if !defined(LPC_BASE_PHY_TX_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_PHY_TX_CLK_SRC CLK_SEL_IDIVC
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#endif
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/**
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* @brief Base APB1 clock enable.
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* @note Base clock for I2C0, I2S, CAN1.
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*/
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#if !defined(LPC_BASE_APB1_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_APB1_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base APB1 clock source.
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*/
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#if !defined(LPC_BASE_APB1_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_APB1_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base APB3 clock enable.
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* @note Base clock for I2C1, DAC, ADC0, ADC1, CAN0.
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*/
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#if !defined(LPC_BASE_APB3_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_APB3_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base APB3 clock source.
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*/
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#if !defined(LPC_BASE_APB3_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_APB3_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base LCD clock enable.
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*/
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#if !defined(LPC_BASE_LCD_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_LCD_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base LCD clock source.
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*/
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#if !defined(LPC_BASE_LCD_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_LCD_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base SDIO clock enable.
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*/
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#if !defined(LPC_BASE_SDIO_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_SDIO_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base SDIO clock source.
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*/
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#if !defined(LPC_BASE_SDIO_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_SDIO_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base SSP0 clock enable.
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*/
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#if !defined(LPC_BASE_SSP0_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_SSP0_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base SSP0 clock source.
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*/
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#if !defined(LPC_BASE_SSP0_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_SSP0_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base SSP1 clock enable.
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*/
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#if !defined(LPC_BASE_SSP1_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_SSP1_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base SSP1 clock source.
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*/
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#if !defined(LPC_BASE_SSP1_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_SSP1_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base UART0 clock enable.
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*/
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#if !defined(LPC_BASE_UART0_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_UART0_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base UART0 clock source.
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*/
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#if !defined(LPC_BASE_UART0_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_UART0_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base UART1 clock enable.
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*/
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#if !defined(LPC_BASE_UART1_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_UART1_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base UART1 clock source.
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*/
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#if !defined(LPC_BASE_UART1_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_UART1_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base UART2 clock enable.
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*/
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#if !defined(LPC_BASE_UART2_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_UART2_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base UART2 clock source.
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*/
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#if !defined(LPC_BASE_UART2_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_UART2_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base UART3 clock enable.
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*/
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#if !defined(LPC_BASE_UART3_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_UART3_CLK_ENABLE TRUE
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#endif
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/**
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* @brief Base UART3 clock source.
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*/
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#if !defined(LPC_BASE_UART3_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_UART3_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base OUT clock enable.
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*/
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#if !defined(LPC_BASE_OUT_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_OUT_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base OUT clock source.
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*/
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#if !defined(LPC_BASE_OUT_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_OUT_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base APLL clock enable.
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*/
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#if !defined(LPC_BASE_APLL_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_APLL_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base APLL clock source.
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*/
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#if !defined(LPC_BASE_APLL_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_APLL_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base CGU OUT0 clock enable.
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*/
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#if !defined(LPC_BASE_CGU_OUT0_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_CGU_OUT0_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base CGU OUT0 clock source.
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*/
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#if !defined(LPC_BASE_CGU_OUT0_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_CGU_OUT0_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief Base CGU OUT1 clock enable.
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*/
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#if !defined(LPC_BASE_CGU_OUT1_CLK_ENABLE) || defined(__DOXYGEN__)
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#define LPC_BASE_CGU_OUT1_CLK_ENABLE FALSE
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#endif
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/**
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* @brief Base CGU OUT1 clock source.
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*/
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#if !defined(LPC_BASE_CGU_OUT1_CLK_SRC) || defined(__DOXYGEN__)
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#define LPC_BASE_CGU_OUT1_CLK_SRC CLK_SEL_IRC
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/**
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* @brief Calculated OSCRANGE setting.
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*/
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#if (XTAL < 18000000) || defined(__DOXYGEN__)
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#define LPC_OSCRANGE 0
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#else
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#define LPC_OSCRANGE 1
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#endif
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/**
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* @brief PLL1 FCLKIN frequency select.
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*/
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#if LPC_XTAL_ENABLE
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#define LPC_PLL1_FCLKIN XTAL
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#else
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#define LPC_PLL1_FCLKIN IRCOSCCLK
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#endif
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/**
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* @brief MSEL mask in PLL1_CTRL register.
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*/
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#if (((LPC_PLL1_MUL) >= 1) && ((LPC_PLL1_MUL) <= 256))|| defined(__DOXYGEN__)
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#define LPC_PLL1_CTRL_MSEL ((LPC_PLL1_MUL) - 1)
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#else
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#error "Invalid LPC_PLL1_MULL value."
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#endif
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/**
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* @brief NSEL mask in PLL1_CTRL register.
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*/
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#if (((LPC_PLL1_PREDIV) >= 1) && ((LPC_PLL1_PREDIV) <= 4)) || defined(__DOXYGEN__)
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#define LPC_PLL1_CTRL_NSEL ((LPC_PLL1_PREDIV) - 1)
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#else
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#error "Invalid LPC_PLL1_PREDIV value (1 to 4 accepted)."
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#endif
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/**
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* @brief PSEL mask in PLL1_CTRL register.
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*/
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#if ((LPC_PLL1_POSTDIV) == 2) || ((LPC_PLL1_POSTDIV) == 4) || ((LPC_PLL1_POSTDIV) == 8) ||\
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((LPC_PLL1_POSTDIV) == 16) || defined(__DOXYGEN__)
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#define LPC_PLL1_CTRL_PSEL (((LPC_PLL1_POSTDIV) / 2) - 1)
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#else
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#error "Invalid LPC_PLL1_POSTDIV value (2, 4, 6, 8 accepted)."
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#endif
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/**
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* @brief CCO frequency.
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*/
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#define LPC_PLL1_CCO (((LPC_PLL1_MUL) * \
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LPC_PLL1_FCLKIN)/(LPC_PLL1_PREDIV))
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#if (LPC_PLL1_CCO < 156000000) || (LPC_PLL1_CCO > 320000000)
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#error "CCO frequency out of the acceptable range (156...320)."
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#endif
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/**
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* @brief PLL1 clock frequency.
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*/
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#if LPC_PLL1_ENABLE && LPC_PLL1_POSTDIV_ENABLE
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#define LPC_PLL1_CLK (LPC_PLL1_CCO / (LPC_PLL1_POSTDIV))
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#elif LPC_PLL1_ENABLE
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#define LPC_PLL1_CLK LPC_PLL1_CCO
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#endif
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/**
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* @brief CPU clock frequency.
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*/
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#if LPC_PLL1_ENABLE
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#define LPC_BASE_M4_CLK LPC_PLL1_CLK
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#define LPC_BASE_M4_CLK_SRC CLK_SEL_PLL1
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#elif LPC_XTAL_ENABLE
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#define LPC_BASE_M4_CLK XTAL
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#define LPC_BASE_M4_CLK_SRC CLK_SEL_XTAL
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#else
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#define LPC_BASE_M4_CLK IRCOSCCLK
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#define LPC_BASE_M4_CLK_SRC CLK_SEL_IRC
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#endif
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/**
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* @brief CPU clock frequency range check.
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* @note Max clock for LPC43xx is 204 MHz.
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*/
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#if (LPC_BASE_M4_CLK > 204000000) || defined(__DOXYGEN__)
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#error "CPU Clock out of range."
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#endif
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#if (!LPC_FLASHLESS) || defined(__DOXYGEN__)
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/**
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* @brief Flash wait states.
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*/
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#if (LPC_BASE_M4_CLK <= 21000000) || defined(__DOXYGEN__)
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#define LPC_FLASHCFG_FLASHTIM 0UL
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#elif LPC_BASE_M4_CLK <= 43000000
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#define LPC_FLASHCFG_FLASHTIM 1UL
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#elif LPC_BASE_M4_CLK <= 64000000
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#define LPC_FLASHCFG_FLASHTIM 2UL
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#elif LPC_BASE_M4_CLK <= 86000000
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#define LPC_FLASHCFG_FLASHTIM 3UL
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#elif LPC_BASE_M4_CLK <= 107000000
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#define LPC_FLASHCFG_FLASHTIM 4UL
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#elif LPC_BASE_M4_CLK <= 129000000
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#define LPC_FLASHCFG_FLASHTIM 5UL
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#elif LPC_BASE_M4_CLK <= 150000000
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#define LPC_FLASHCFG_FLASHTIM 6UL
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#elif LPC_BASE_M4_CLK <= 172000000
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#define LPC_FLASHCFG_FLASHTIM 7UL
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#elif LPC_BASE_M4_CLK <= 193000000
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#define LPC_FLASHCFG_FLASHTIM 8UL
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#else
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#define LPC_FLASHCFG_FLASHTIM 9UL
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#endif
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#endif
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/**
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* @brief CPU clock frequency.
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*/
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#if LPC_IDIVA_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_IDIVA_CLK RTC_XTAL/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IRC
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#define LPC_IDIVA_CLK IRCOSCCLK/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_IDIVA_CLK ENET_RX_CLK/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_IDIVA_CLK ENET_TX_CLK/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_IDIVA_CLK GP_CLKIN_CLK/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_XTAL
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#define LPC_IDIVA_CLK XTAL/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_PLL0USB
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#error "LPC_IDIVA_CLK source can't be PLL0USB."
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_IDIVA_CLK LPC_PLL0AUDIO_CLK/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_PLL1
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#define LPC_IDIVA_CLK LPC_PLL1_CLK/LPC_IDIVA_DIV
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVA
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#error "LPC_IDIVA_CLK source can't be IDIVA_CLK."
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVB
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#error "LPC_IDIVA_CLK source can't be IDIVB_CLK."
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVC
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#error "LPC_IDIVA_CLK source can't be IDIVC_CLK."
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVD
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#error "LPC_IDIVA_CLK source can't be IDIVD_CLK."
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#elif LPC_IDIVA_CLK_SRC == CLK_SEL_IDIVE
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#error "LPC_IDIVA_CLK source can't be IDIVE_CLK."
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#else
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#error "LPC_IDIVA_CLK wrong clock source."
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#endif
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#if LPC_IDIVB_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_IDIVB_CLK RTC_XTAL/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IRC
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#define LPC_IDIVB_CLK IRCOSCCLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_IDIVB_CLK ENET_RX_CLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_IDIVB_CLK ENET_TX_CLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_IDIVB_CLK GP_CLKIN_CLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_XTAL
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#define LPC_IDIVB_CLK XTAL/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_PLL0USB
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#error "LPC_IDIVB_CLK source can't be PLL0USB."
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_IDIVB_CLK LPC_PLL0AUDIO_CLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_PLL1
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#define LPC_IDIVB_CLK LPC_PLL1_CLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVA
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#define LPC_IDIVB_CLK LPC_IDIVA_CLK/LPC_IDIVB_DIV
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVB
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#error "LPC_IDIVB_CLK source can't be IDIVB_CLK."
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVC
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#error "LPC_IDIVB_CLK source can't be IDIVC_CLK."
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVD
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#error "LPC_IDIVB_CLK source can't be IDIVD_CLK."
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#elif LPC_IDIVB_CLK_SRC == CLK_SEL_IDIVE
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#error "LPC_IDIVB_CLK source can't be IDIVE_CLK."
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#else
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#error "LPC_IDIVB_CLK wrong clock source."
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#endif
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#if LPC_IDIVC_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_IDIVC_CLK RTC_XTAL/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IRC
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#define LPC_IDIVC_CLK IRCOSCCLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_IDIVC_CLK ENET_RX_CLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_IDIVC_CLK ENET_TX_CLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_IDIVC_CLK GP_CLKIN_CLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_XTAL
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#define LPC_IDIVC_CLK XTAL/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_PLL0USB
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#error "LPC_IDIVC_CLK source can't be PLL0USB."
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_IDIVC_CLK LPC_PLL0AUDIO_CLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_PLL1
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#define LPC_IDIVC_CLK LPC_PLL1_CLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVA
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#define LPC_IDIVC_CLK LPC_IDIVA_CLK/LPC_IDIVC_DIV
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVB
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#error "LPC_IDIVC_CLK source can't be IDIVB_CLK."
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVC
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#error "LPC_IDIVC_CLK source can't be IDIVC_CLK."
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVD
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#error "LPC_IDIVC_CLK source can't be IDIVD_CLK."
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#elif LPC_IDIVC_CLK_SRC == CLK_SEL_IDIVE
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#error "LPC_IDIVC_CLK source can't be IDIVE_CLK."
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#else
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#error "LPC_IDIVC_CLK wrong clock source."
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#endif
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#if LPC_IDIVD_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_IDIVD_CLK RTC_XTAL/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IRC
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#define LPC_IDIVD_CLK IRCOSCCLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_IDIVD_CLK ENET_RX_CLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_IDIVD_CLK ENET_TX_CLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_IDIVD_CLK GP_CLKIN_CLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_XTAL
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#define LPC_IDIVD_CLK XTAL/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_PLL0USB
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#error "LPC_IDIVD_CLK source can't be PLL0USB."
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_IDIVD_CLK LPC_PLL0AUDIO_CLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_PLL1
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#define LPC_IDIVD_CLK LPC_PLL1_CLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVA
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#define LPC_IDIVD_CLK LPC_IDIVA_CLK/LPC_IDIVD_DIV
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVB
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#error "LPC_IDIVD_CLK source can't be IDIVB_CLK."
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVC
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#error "LPC_IDIVD_CLK source can't be IDIVC_CLK."
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVD
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#error "LPC_IDIVD_CLK source can't be IDIVD_CLK."
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#elif LPC_IDIVD_CLK_SRC == CLK_SEL_IDIVE
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#error "LPC_IDIVD_CLK source can't be IDIVE_CLK."
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#else
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#error "LPC_IDIVD_CLK wrong clock source."
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#endif
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#if LPC_IDIVE_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_IDIVE_CLK RTC_XTAL/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IRC
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#define LPC_IDIVE_CLK IRCOSCCLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_IDIVE_CLK ENET_RX_CLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_IDIVE_CLK ENET_TX_CLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_IDIVE_CLK GP_CLKIN_CLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_XTAL
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#define LPC_IDIVE_CLK XTAL/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_PLL0USB
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#error "LPC_IDIVE_CLK source can't be PLL0USB."
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_IDIVE_CLK LPC_PLL0AUDIO_CLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_PLL1
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#define LPC_IDIVE_CLK LPC_PLL1_CLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVA
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#define LPC_IDIVE_CLK LPC_IDIVA_CLK/LPC_IDIVE_DIV
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVB
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#error "LPC_IDIVE_CLK source can't be IDIVB_CLK."
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVC
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#error "LPC_IDIVE_CLK source can't be IDIVC_CLK."
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVD
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#error "LPC_IDIVE_CLK source can't be IDIVD_CLK."
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#elif LPC_IDIVE_CLK_SRC == CLK_SEL_IDIVE
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#error "LPC_IDIVE_CLK source can't be IDIVE_CLK."
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#else
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#error "LPC_IDIVE_CLK wrong clock source."
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#endif
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/**
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* @brief Peripheral clocks frequency.
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*/
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#if LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_BASE_PERIPH_CLK RTC_XTAL
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IRC
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#define LPC_BASE_PERIPH_CLK IRCOSCCLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_BASE_PERIPH_CLK ENET_RX_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_BASE_PERIPH_CLK ENET_TX_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_BASE_PERIPH_CLK GP_CLKIN_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_XTAL
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#define LPC_BASE_PERIPH_CLK XTAL
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_PLL0USB
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#error "LPC_BASE_PERIPH_CLK source can't be PLL0USB."
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_BASE_PERIPH_CLK LPC_PLL0AUDIO_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_PLL1
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#define LPC_BASE_PERIPH_CLK LPC_PLL1_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVA
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#define LPC_BASE_PERIPH_CLK LPC_IDIVA_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVB
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#define LPC_BASE_PERIPH_CLK LPC_IDIVB_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVC
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#define LPC_BASE_PERIPH_CLK LPC_IDIVC_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVD
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#define LPC_BASE_PERIPH_CLK LPC_IDIVD_CLK
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#elif LPC_BASE_PERIPH_CLK_SRC == CLK_SEL_IDIVE
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#define LPC_BASE_PERIPH_CLK LPC_IDIVE_CLK
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#else
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#error "LPC_BASE_PERIPH_CLK wrong clock source."
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#endif
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#if LPC_BASE_USB1_CLK_SRC == CLK_SEL_32KHZ
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#define LPC_BASE_USB1_CLK RTC_XTAL
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IRC
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#define LPC_BASE_USB1_CLK IRCOSCCLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_ENET_RX_CLK
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#define LPC_BASE_USB1_CLK ENET_RX_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_ENET_TX_CLK
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#define LPC_BASE_USB1_CLK ENET_TX_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_GP_CLKIN
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#define LPC_BASE_USB1_CLK GP_CLKIN_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_XTAL
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#define LPC_BASE_USB1_CLK XTAL
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_PLL0USB
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#define LPC_BASE_USB1_CLK LPC_PLL0USB_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_PLL0AUDIO
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#define LPC_BASE_USB1_CLK LPC_PLL0AUDIO_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_PLL1
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#define LPC_BASE_USB1_CLK LPC_PLL1_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVA
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#define LPC_BASE_USB1_CLK LPC_IDIVA_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVB
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#define LPC_BASE_USB1_CLK LPC_IDIVB_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVC
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#define LPC_BASE_USB1_CLK LPC_IDIVC_CLK
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVD
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#define LPC_BASE_USB1_CLK LPC_IDIVD_CLK
|
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#elif LPC_BASE_USB1_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_USB1_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_USB1_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_SPIFI_CLK RTC_XTAL
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_SPIFI_CLK IRCOSCCLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_SPIFI_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_SPIFI_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_SPIFI_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_SPIFI_CLK XTAL
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_SPIFI_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_SPIFI_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_SPIFI_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_SPIFI_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_SPIFI_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_SPIFI_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_SPIFI_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_SPIFI_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_SPIFI_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_SPIFI_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_SPI_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_SPI_CLK RTC_XTAL
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_SPI_CLK IRCOSCCLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_SPI_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_SPI_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_SPI_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_SPI_CLK XTAL
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_SPI_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_SPI_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_SPI_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_SPI_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_SPI_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_SPI_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_SPI_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_SPI_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_SPI_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_SPI_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_PHY_RX_CLK RTC_XTAL
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_PHY_RX_CLK IRCOSCCLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_PHY_RX_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_PHY_RX_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_PHY_RX_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_PHY_RX_CLK XTAL
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_PHY_RX_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_PHY_RX_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_PHY_RX_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_PHY_RX_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_PHY_RX_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_PHY_RX_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_PHY_RX_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_PHY_RX_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_PHY_RX_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_PHY_RX_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_PHY_TX_CLK RTC_XTAL
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_PHY_TX_CLK IRCOSCCLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_PHY_TX_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_PHY_TX_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_PHY_TX_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_PHY_TX_CLK XTAL
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_PHY_TX_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_PHY_TX_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_PHY_TX_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_PHY_TX_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_PHY_TX_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_PHY_TX_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_PHY_TX_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_PHY_TX_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_PHY_TX_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_PHY_TX_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_APB1_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_APB1_CLK RTC_XTAL
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_APB1_CLK IRCOSCCLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_APB1_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_APB1_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_APB1_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_APB1_CLK XTAL
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_APB1_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_APB1_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_APB1_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_APB1_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_APB1_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_APB1_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_APB1_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_APB1_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_APB1_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_APB1_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_APB3_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_APB3_CLK RTC_XTAL
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_APB3_CLK IRCOSCCLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_APB3_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_APB3_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_APB3_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_APB3_CLK XTAL
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_APB3_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_APB3_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_APB3_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_APB3_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_APB3_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_APB3_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_APB3_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_APB3_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_APB3_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_APB3_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_LCD_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_LCD_CLK RTC_XTAL
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_LCD_CLK IRCOSCCLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_LCD_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_LCD_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_LCD_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_LCD_CLK XTAL
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_LCD_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_LCD_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_LCD_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_LCD_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_LCD_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_LCD_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_LCD_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_LCD_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_LCD_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_LCD_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_SDIO_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_SDIO_CLK RTC_XTAL
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_SDIO_CLK IRCOSCCLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_SDIO_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_SDIO_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_SDIO_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_SDIO_CLK XTAL
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_SDIO_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_SDIO_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_SDIO_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_SDIO_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_SDIO_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_SDIO_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_SDIO_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_SDIO_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_SDIO_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_SDIO_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_SSP0_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_SSP0_CLK RTC_XTAL
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_SSP0_CLK IRCOSCCLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_SSP0_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_SSP0_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_SSP0_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_SSP0_CLK XTAL
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_SSP0_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_SSP0_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_SSP0_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_SSP0_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_SSP0_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_SSP0_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_SSP0_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_SSP0_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_SSP0_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_SSP0_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_SSP1_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_SSP1_CLK RTC_XTAL
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_SSP1_CLK IRCOSCCLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_SSP1_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_SSP1_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_SSP1_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_SSP1_CLK XTAL
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_SSP1_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_SSP1_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_SSP1_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_SSP1_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_SSP1_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_SSP1_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_SSP1_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_SSP1_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_SSP1_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_SSP1_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_UART0_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_UART0_CLK RTC_XTAL
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_UART0_CLK IRCOSCCLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_UART0_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_UART0_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_UART0_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_UART0_CLK XTAL
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_UART0_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_UART0_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_UART0_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_UART0_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_UART0_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_UART0_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_UART0_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_UART0_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_UART0_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_UART0_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_UART1_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_UART1_CLK RTC_XTAL
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_UART1_CLK IRCOSCCLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_UART1_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_UART1_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_UART1_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_UART1_CLK XTAL
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_UART1_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_UART1_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_UART1_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_UART1_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_UART1_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_UART1_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_UART1_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_UART1_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_UART1_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_UART1_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_UART2_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_UART2_CLK RTC_XTAL
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_UART2_CLK IRCOSCCLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_UART2_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_UART2_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_UART2_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_UART2_CLK XTAL
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_UART2_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_UART2_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_UART2_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_UART2_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_UART2_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_UART2_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_UART2_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_UART2_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_UART2_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_UART2_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_UART3_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_UART3_CLK RTC_XTAL
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_UART3_CLK IRCOSCCLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_UART3_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_UART3_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_UART3_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_UART3_CLK XTAL
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_UART3_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_UART3_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_UART3_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_UART3_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_UART3_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_UART3_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_UART3_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_UART3_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_UART3_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_UART3_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_OUT_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_OUT_CLK RTC_XTAL
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_OUT_CLK IRCOSCCLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_OUT_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_OUT_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_OUT_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_OUT_CLK XTAL
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_OUT_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_OUT_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_OUT_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_OUT_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_OUT_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_OUT_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_OUT_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_OUT_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_OUT_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_OUT_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_APLL_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_APLL_CLK RTC_XTAL
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_APLL_CLK IRCOSCCLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_APLL_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_APLL_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_APLL_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_APLL_CLK XTAL
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_APLL_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_APLL_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_APLL_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_APLL_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_APLL_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_APLL_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_APLL_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_APLL_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_APLL_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_APLL_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_CGU_OUT0_CLK RTC_XTAL
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_CGU_OUT0_CLK IRCOSCCLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_CGU_OUT0_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_CGU_OUT0_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_CGU_OUT0_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_CGU_OUT0_CLK XTAL
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_CGU_OUT0_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_CGU_OUT0_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_CGU_OUT0_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_CGU_OUT0_CLK wrong clock source."
|
|
#endif
|
|
|
|
#if LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_32KHZ
|
|
#define LPC_BASE_CGU_OUT1_CLK RTC_XTAL
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IRC
|
|
#define LPC_BASE_CGU_OUT1_CLK IRCOSCCLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_ENET_RX_CLK
|
|
#define LPC_BASE_CGU_OUT1_CLK ENET_RX_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_ENET_TX_CLK
|
|
#define LPC_BASE_CGU_OUT1_CLK ENET_TX_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_GP_CLKIN
|
|
#define LPC_BASE_CGU_OUT1_CLK GP_CLKIN_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_XTAL
|
|
#define LPC_BASE_CGU_OUT1_CLK XTAL
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_PLL0USB
|
|
#error "LPC_BASE_CGU_OUT1_CLK source can't be PLL0USB."
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_PLL0AUDIO
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_PLL0AUDIO_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_PLL1
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_PLL1_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVA
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_IDIVA_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVB
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_IDIVB_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVC
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_IDIVC_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVD
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_IDIVD_CLK
|
|
#elif LPC_BASE_CGU_OUT1_CLK_SRC == CLK_SEL_IDIVE
|
|
#define LPC_BASE_CGU_OUT1_CLK LPC_IDIVE_CLK
|
|
#else
|
|
#error "LPC_BASE_CGU_OUT1_CLK wrong clock source."
|
|
#endif
|
|
|
|
#define LPC_CLK_M4_ETHERNET LPC_BASE_M4_CLK
|
|
/*===========================================================================*/
|
|
/* Driver data structures and types. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @brief Type of the realtime free counter value.
|
|
*/
|
|
typedef uint32_t halrtcnt_t;
|
|
|
|
/*===========================================================================*/
|
|
/* Driver macros. */
|
|
/*===========================================================================*/
|
|
|
|
/**
|
|
* @brief Returns the current value of the system free running counter.
|
|
* @note This service is implemented by returning the content of the
|
|
* DWT_CYCCNT register.
|
|
*
|
|
* @return The value of the system free running counter of
|
|
* type halrtcnt_t.
|
|
*
|
|
* @notapi
|
|
*/
|
|
#define hal_lld_get_counter_value() DWT_CYCCNT
|
|
|
|
/**
|
|
* @brief Realtime counter frequency.
|
|
* @note The DWT_CYCCNT register is incremented directly by the cpu
|
|
* clock so this function returns LPC_BASE_M4_CLK.
|
|
*
|
|
* @return The realtime counter frequency of type halclock_t.
|
|
*
|
|
* @notapi
|
|
*/
|
|
#define hal_lld_get_counter_frequency() LPC_BASE_M4_CLK
|
|
|
|
/*===========================================================================*/
|
|
/* External declarations. */
|
|
/*===========================================================================*/
|
|
|
|
#include "lpc43xx_dma.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
void hal_lld_init(void);
|
|
void lpc_clock_init(void);
|
|
void lpc_deep_sleep_enter(uint32_t core_type);
|
|
void lpc_deep_sleep_exit(void);
|
|
void lpc_deep_power_down_enter(uint32_t core_type);
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HAL_LLD_H_ */
|
|
|
|
/** @} */
|