63 lines
1.8 KiB
C
63 lines
1.8 KiB
C
/******************************************************************************
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* @file: system_LPC8xx.h
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* @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
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* for the NXP LPC8xx Device Series
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* @version: V1.0
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* @date: 16. Aug. 2012
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*----------------------------------------------------------------------------
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*
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* Copyright (C) 2012 ARM Limited. All rights reserved.
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*
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* ARM Limited (ARM) is supplying this software for use with Cortex-M0+
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __SYSTEM_LPC8xx_H
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#define __SYSTEM_LPC8xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit (void);
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/**
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* Update SystemCoreClock variable
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*
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* @param none
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* @return none
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*
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* @brief Updates the SystemCoreClock with current core Clock
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* retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_LPC8xx_H */
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