317 lines
7.3 KiB
C
317 lines
7.3 KiB
C
/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file eTimer_v1/etimer.h
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* @brief SPC5xx eTimer header file.
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*
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* @addtogroup ICU
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* @{
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*/
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#ifndef _ETIMER_H_
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#define _ETIMER_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief SPC5 FlexPWM registers block.
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* @note Redefined from the SPC5 headers because the non uniform
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* declaration of the SubModules registers among the various
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* sub-families.
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*/
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struct spc5_etimer_submodule {
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union {
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vuint16_t R;
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struct {
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vuint16_t COMP1 :16;
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} B;
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} COMP1; /* Compare Register 1 */
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union {
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vuint16_t R;
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struct {
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vuint16_t COMP2 :16;
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} B;
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} COMP2; /* Compare Register 2 */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPT1 :16;
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} B;
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} CAPT1; /* Capture Register 1 */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPT2 :16;
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} B;
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} CAPT2; /* Capture Register 2 */
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union {
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vuint16_t R;
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struct {
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vuint16_t LOAD :16;
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} B;
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} LOAD; /* Load Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t HOLD :16;
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} B;
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} HOLD; /* Hold Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CNTR :16;
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} B;
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} CNTR; /* Counter Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CNTMODE :3;
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vuint16_t PRISRC :5;
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vuint16_t ONCE :1;
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vuint16_t LENGTH :1;
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vuint16_t DIR :1;
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vuint16_t SECSRC :5;
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} B;
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} CTRL; /* Control Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t OEN :1;
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vuint16_t RDNT :1;
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vuint16_t INPUT :1;
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vuint16_t VAL :1;
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vuint16_t FORCE :1;
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vuint16_t COFRC :1;
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vuint16_t COINIT :2;
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vuint16_t SIPS :1;
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vuint16_t PIPS :1;
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vuint16_t OPS :1;
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vuint16_t MSTR :1;
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vuint16_t OUTMODE :4;
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} B;
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} CTRL2; /* Control Register 2 */
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union {
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vuint16_t R;
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struct {
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vuint16_t STPEN :1;
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vuint16_t ROC :2;
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vuint16_t FMODE :1;
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vuint16_t FDIS :4;
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vuint16_t C2FCNT :3;
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vuint16_t C1FCNT :3;
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vuint16_t DBGEN :2;
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} B;
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} CTRL3; /* Control Register 3 */
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union {
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vuint16_t R;
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struct {
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vuint16_t :6;
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vuint16_t WDF :1;
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vuint16_t RCF :1;
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vuint16_t ICF2 :1;
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vuint16_t ICF1 :1;
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vuint16_t IEHF :1;
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vuint16_t IELF :1;
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vuint16_t TOF :1;
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vuint16_t TCF2 :1;
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vuint16_t TCF1 :1;
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vuint16_t TCF :1;
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} B;
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} STS; /* Status Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t ICF2DE :1;
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vuint16_t ICF1DE :1;
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vuint16_t CMPLD2DE :1;
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vuint16_t CMPLD1DE :1;
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vuint16_t :2;
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vuint16_t WDFIE :1;
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vuint16_t RCFIE :1;
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vuint16_t ICF2IE :1;
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vuint16_t ICF1IE :1;
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vuint16_t IEHFIE :1;
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vuint16_t IELFIE :1;
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vuint16_t TOFIE :1;
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vuint16_t TCF2IE :1;
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vuint16_t TCF1IE :1;
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vuint16_t TCFIE :1;
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} B;
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} INTDMA; /* Interrupt and DMA Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CMPLD1 :16;
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} B;
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} CMPLD1; /* Compare Load Register 1 */
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union {
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vuint16_t R;
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struct {
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vuint16_t CMPLD2 :16;
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} B;
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} CMPLD2; /* Compare Load Register 2 */
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union {
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vuint16_t R;
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struct {
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vuint16_t CLC2 :3;
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vuint16_t CLC1 :3;
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vuint16_t CMPMODE :2;
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vuint16_t CPT2MODE :2;
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vuint16_t CPT1MODE :2;
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vuint16_t CFWM :2;
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vuint16_t ONESHOT :1;
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vuint16_t ARM :1;
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} B;
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} CCCTRL; /* Compare and Capture Control Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :5;
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vuint16_t FILTCNT :3;
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vuint16_t FILTPER :8;
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} B;
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} FILT; /* Input Filter Register */
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};
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/* end of ETIMER_CHANNEL_tag */
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struct spc5_etimer {
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struct spc5_etimer_submodule CHANNEL[8];
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union {
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vuint16_t R;
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struct {
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vuint16_t WDTOL :16;
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} B;
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} WDTOL; /* Watchdog Time-out Low Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t WDTOH :16;
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} B;
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} WDTOH; /* Watchdog Time-out High Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :3;
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vuint16_t FTEST :1;
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vuint16_t FIE :4;
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vuint16_t :4;
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vuint16_t FLVL :4;
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} B;
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} FCTRL; /* Fault Control Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :4;
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vuint16_t FFPIN :4;
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vuint16_t :4;
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vuint16_t FFLAG :4;
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} B;
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} FSTS; /* Fault Status Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :5;
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vuint16_t FFILTCNT :3;
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vuint16_t FFILTPER :8;
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} B;
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} FFILT; /* Fault Filter Register */
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int16_t ETIMER_reserved1;
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union {
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vuint16_t R;
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struct {
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vuint16_t :8;
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vuint16_t ENBL :8;
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} B;
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} ENBL; /* Channel Enable Register */
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int16_t ETIMER_reserved2;
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union {
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vuint16_t R;
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struct {
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vuint16_t :11;
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vuint16_t DREQ :5;
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} B;
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} DREQ[4]; /* DMA Request 0->3 Select Register */
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};
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/* end of ETIMER_tag */
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name FlexPWM units references
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* @{
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*/
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#if SPC5_HAS_ETIMER0
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#define SPC5_ETIMER_0 (*(volatile struct spc5_etimer *)0xFFE18000UL)
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#endif
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#if SPC5_HAS_ETIMER1
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#define SPC5_ETIMER_1 (*(volatile struct spc5_etimer *)0xFFE1C000UL)
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#endif
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#if SPC5_HAS_ETIMER2
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#define SPC5_ETIMER_2 (*(volatile struct spc5_etimer *)0xFFE20000UL)
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#endif
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/** @} */
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#endif /* _FLEXPWM_H_ */
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/** @} */
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