528 lines
15 KiB
C
528 lines
15 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/pwm_lld.c
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* @brief STM32 PWM subsystem low level driver header.
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*
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* @addtogroup PWM
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PWM || defined(__DOXYGEN__)
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/* There are differences in vector names in the ST header for devices
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including TIM15, TIM16, TIM17.*/
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#if STM32_HAS_TIM15
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#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
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#endif
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#if STM32_HAS_TIM16
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#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
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#endif
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#if STM32_HAS_TIM17
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#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief PWM1 driver identifier.
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* @note The driver PWM1 allocates the complex timer TIM1 when enabled.
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*/
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#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__)
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PWMDriver PWMD1;
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#endif
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/**
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* @brief PWM2 driver identifier.
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* @note The driver PWM2 allocates the timer TIM2 when enabled.
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*/
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#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__)
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PWMDriver PWMD2;
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#endif
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/**
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* @brief PWM3 driver identifier.
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* @note The driver PWM3 allocates the timer TIM3 when enabled.
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*/
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#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__)
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PWMDriver PWMD3;
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#endif
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/**
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* @brief PWM4 driver identifier.
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* @note The driver PWM4 allocates the timer TIM4 when enabled.
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*/
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#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__)
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PWMDriver PWMD4;
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#endif
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/**
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* @brief PWM5 driver identifier.
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* @note The driver PWM5 allocates the timer TIM5 when enabled.
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*/
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#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)
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PWMDriver PWMD5;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 || \
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STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)
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/**
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* @brief Common TIM2...TIM5 IRQ handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*/
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static void serve_interrupt(PWMDriver *pwmp) {
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uint16_t sr;
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sr = pwmp->tim->SR;
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sr &= pwmp->tim->DIER;
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pwmp->tim->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF |
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TIM_SR_CC4IF | TIM_SR_UIF);
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if ((sr & TIM_SR_CC1IF) != 0)
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pwmp->config->channels[0].callback(pwmp);
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if ((sr & TIM_SR_CC2IF) != 0)
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pwmp->config->channels[1].callback(pwmp);
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if ((sr & TIM_SR_CC3IF) != 0)
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pwmp->config->channels[2].callback(pwmp);
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if ((sr & TIM_SR_CC4IF) != 0)
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pwmp->config->channels[3].callback(pwmp);
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if ((sr & TIM_SR_UIF) != 0)
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pwmp->config->callback(pwmp);
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}
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#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_PWM_USE_TIM1
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/**
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* @brief TIM1 update interrupt handler.
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* @note It is assumed that this interrupt is only activated if the callback
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* pointer is not equal to @p NULL in order to not perform an extra
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* check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TIM1_UP_IRQHandler) {
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CH_IRQ_PROLOGUE();
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TIM1->SR = ~TIM_SR_UIF;
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PWMD1.config->callback(&PWMD1);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1 compare interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TIM1_CC_IRQHandler) {
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uint16_t sr;
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CH_IRQ_PROLOGUE();
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sr = TIM1->SR & TIM1->DIER;
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TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);
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if ((sr & TIM_SR_CC1IF) != 0)
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PWMD1.config->channels[0].callback(&PWMD1);
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if ((sr & TIM_SR_CC2IF) != 0)
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PWMD1.config->channels[1].callback(&PWMD1);
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if ((sr & TIM_SR_CC3IF) != 0)
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PWMD1.config->channels[2].callback(&PWMD1);
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if ((sr & TIM_SR_CC4IF) != 0)
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PWMD1.config->channels[3].callback(&PWMD1);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_PWM_USE_TIM1 */
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#if STM32_PWM_USE_TIM2
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/**
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* @brief TIM2 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TIM2_IRQHandler) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&PWMD2);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_PWM_USE_TIM2 */
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#if STM32_PWM_USE_TIM3
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/**
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* @brief TIM3 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TIM3_IRQHandler) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&PWMD3);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_PWM_USE_TIM3 */
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#if STM32_PWM_USE_TIM4
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/**
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* @brief TIM4 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TIM4_IRQHandler) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&PWMD4);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_PWM_USE_TIM4 */
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#if STM32_PWM_USE_TIM5
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/**
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* @brief TIM5 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(TIM5_IRQHandler) {
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CH_IRQ_PROLOGUE();
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serve_interrupt(&PWMD5);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_PWM_USE_TIM5 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level PWM driver initialization.
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*
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* @notapi
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*/
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void pwm_lld_init(void) {
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#if STM32_PWM_USE_TIM1
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/* Driver initialization.*/
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pwmObjectInit(&PWMD1);
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PWMD1.enabled_channels = 0;
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PWMD1.tim = TIM1;
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#endif
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#if STM32_PWM_USE_TIM2
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/* Driver initialization.*/
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pwmObjectInit(&PWMD2);
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PWMD2.enabled_channels = 0;
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PWMD2.tim = TIM2;
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#endif
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#if STM32_PWM_USE_TIM3
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/* Driver initialization.*/
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pwmObjectInit(&PWMD3);
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PWMD3.enabled_channels = 0;
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PWMD3.tim = TIM3;
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#endif
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#if STM32_PWM_USE_TIM4
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/* Driver initialization.*/
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pwmObjectInit(&PWMD4);
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PWMD4.enabled_channels = 0;
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PWMD4.tim = TIM4;
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#endif
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#if STM32_PWM_USE_TIM5
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/* Driver initialization.*/
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pwmObjectInit(&PWMD5);
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PWMD5.enabled_channels = 0;
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PWMD5.tim = TIM5;
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#endif
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}
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/**
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* @brief Configures and activates the PWM peripheral.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*
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* @notapi
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*/
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void pwm_lld_start(PWMDriver *pwmp) {
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uint16_t ccer;
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/* Reset channels.*/
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pwmp->enabled_channels = 0; /* All channels disabled. */
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if (pwmp->state == PWM_STOP) {
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/* Clock activation and timer reset.*/
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#if STM32_PWM_USE_TIM1
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if (&PWMD1 == pwmp) {
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
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RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
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RCC->APB2RSTR = 0;
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NVICEnableVector(TIM1_UP_IRQn,
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CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
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NVICEnableVector(TIM1_CC_IRQn,
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CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
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}
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#endif
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#if STM32_PWM_USE_TIM2
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if (&PWMD2 == pwmp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;
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RCC->APB1RSTR = 0;
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NVICEnableVector(TIM2_IRQn,
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CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
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}
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#endif
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#if STM32_PWM_USE_TIM3
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if (&PWMD3 == pwmp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
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RCC->APB1RSTR = 0;
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NVICEnableVector(TIM3_IRQn,
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CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
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}
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#endif
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#if STM32_PWM_USE_TIM4
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if (&PWMD4 == pwmp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
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RCC->APB1RSTR = 0;
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NVICEnableVector(TIM4_IRQn,
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CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
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}
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#endif
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#if STM32_PWM_USE_TIM5
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if (&PWMD5 == pwmp) {
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RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
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RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
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RCC->APB1RSTR = 0;
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NVICEnableVector(TIM5_IRQn,
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CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
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}
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#endif
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/* All channels configured in PWM1 mode with preload enabled and will
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stay that way until the driver is stopped.*/
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pwmp->tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
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TIM_CCMR1_OC1PE |
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TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 |
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TIM_CCMR1_OC2PE;
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pwmp->tim->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
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TIM_CCMR2_OC3PE |
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TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 |
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TIM_CCMR2_OC4PE;
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}
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else {
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/* Driver re-configuration scenario, it must be stopped first.*/
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/* Really required ?????????? */
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pwmp->tim->CR1 = 0; /* Timer stopped. */
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pwmp->tim->CR2 = 0; /* Timer stopped. */
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pwmp->tim->SMCR = 0; /* Slave mode disabled. */
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pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */
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pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */
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pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */
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pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */
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pwmp->tim->CNT = 0;
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}
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/* Timer configuration.*/
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pwmp->tim->CR2 = pwmp->config->cr2;
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pwmp->tim->PSC = pwmp->config->psc;
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pwmp->tim->ARR = pwmp->config->arr;
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/* Output enables and polarities setup.*/
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ccer = 0;
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switch (pwmp->config->channels[0].mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC1P;
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC1E;
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default:
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;
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}
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switch (pwmp->config->channels[1].mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC2P;
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC2E;
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default:
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;
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}
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switch (pwmp->config->channels[2].mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC3P;
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC3E;
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default:
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;
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}
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switch (pwmp->config->channels[3].mode) {
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case PWM_OUTPUT_ACTIVE_LOW:
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ccer |= TIM_CCER_CC4P;
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case PWM_OUTPUT_ACTIVE_HIGH:
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ccer |= TIM_CCER_CC4E;
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default:
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;
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}
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pwmp->tim->CCER = ccer;
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pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */
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pwmp->tim->SR = 0; /* Clear pending IRQs. */
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pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : TIM_DIER_UIE;
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pwmp->tim->BDTR = TIM_BDTR_MOE;
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/* Timer configured and started.*/
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pwmp->tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN;
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}
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/**
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* @brief Deactivates the PWM peripheral.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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*
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* @notapi
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*/
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void pwm_lld_stop(PWMDriver *pwmp) {
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/* If in ready state then disables the PWM clock.*/
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if (pwmp->state == PWM_READY) {
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pwmp->enabled_channels = 0; /* All channels disabled. */
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pwmp->tim->CR1 = 0;
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pwmp->tim->CR2 = 0;
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pwmp->tim->CCER = 0; /* Outputs disabled. */
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pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */
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pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */
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pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */
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pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */
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pwmp->tim->BDTR = 0;
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pwmp->tim->DIER = 0;
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pwmp->tim->SR = 0;
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pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */
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#if STM32_PWM_USE_TIM1
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if (&PWMD1 == pwmp) {
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NVICDisableVector(TIM1_UP_IRQn);
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NVICDisableVector(TIM1_CC_IRQn);
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;
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}
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#endif
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#if STM32_PWM_USE_TIM2
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if (&PWMD2 == pwmp) {
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NVICDisableVector(TIM2_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
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}
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#endif
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#if STM32_PWM_USE_TIM3
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if (&PWMD3 == pwmp) {
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NVICDisableVector(TIM3_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;
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}
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#endif
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#if STM32_PWM_USE_TIM4
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if (&PWMD4 == pwmp) {
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NVICDisableVector(TIM4_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
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}
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#endif
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#if STM32_PWM_USE_TIM5
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if (&PWMD5 == pwmp) {
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NVICDisableVector(TIM5_IRQn);
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
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}
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#endif
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}
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}
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/**
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* @brief Enables a PWM channel.
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*
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* @param[in] pwmp pointer to a @p PWMDriver object
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* @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
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* @param[in] width PWM pulse width as clock pulses number
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*
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* @notapi
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*/
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void pwm_lld_enable_channel(PWMDriver *pwmp,
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pwmchannel_t channel,
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pwmcnt_t width) {
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*(&pwmp->tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */
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if ((pwmp->enabled_channels & (1 << channel)) == 0) {
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/* The channel is not enabled yet.*/
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|
pwmp->enabled_channels |= (1 << channel);
|
|
/* If there is a callback associated to the channel then the proper
|
|
interrupt is cleared and enabled.*/
|
|
if (pwmp->config->channels[channel].callback) {
|
|
pwmp->tim->SR = ~(2 << channel);
|
|
pwmp->tim->DIER |= (2 << channel);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Disables a PWM channel.
|
|
* @details The channel is disabled and its output line returned to the
|
|
* idle state.
|
|
*
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
|
* @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
|
|
*
|
|
* @notapi
|
|
*/
|
|
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
|
|
|
|
*(&pwmp->tim->CCR1 + (channel * 2)) = 0;
|
|
pwmp->tim->DIER &= ~(2 << channel);
|
|
pwmp->enabled_channels &= ~(1 << channel);
|
|
}
|
|
|
|
#endif /* HAL_USE_PWM */
|
|
|
|
/** @} */
|