307 lines
17 KiB
C
307 lines
17 KiB
C
/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC560BCxx/spc560bc_registry.h
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* @brief SPC560B/Cxx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _SPC560BC_REGISTRY_H_
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#define _SPC560BC_REGISTRY_H_
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name SPC560B/Cxx capabilities
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* @{
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*/
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/* eDMA attributes.*/
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#define SPC5_HAS_EDMA FALSE
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/* LINFlex attributes.*/
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#define SPC5_HAS_LINFLEX0 TRUE
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#define SPC5_LINFLEX0_PCTL 48
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#define SPC5_LINFLEX0_RXI_HANDLER vector79
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#define SPC5_LINFLEX0_TXI_HANDLER vector80
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#define SPC5_LINFLEX0_ERR_HANDLER vector81
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#define SPC5_LINFLEX0_RXI_NUMBER 79
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#define SPC5_LINFLEX0_TXI_NUMBER 80
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#define SPC5_LINFLEX0_ERR_NUMBER 81
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#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX1 TRUE
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#define SPC5_LINFLEX1_PCTL 49
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#define SPC5_LINFLEX1_RXI_HANDLER vector99
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#define SPC5_LINFLEX1_TXI_HANDLER vector100
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#define SPC5_LINFLEX1_ERR_HANDLER vector101
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#define SPC5_LINFLEX1_RXI_NUMBER 99
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#define SPC5_LINFLEX1_TXI_NUMBER 100
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#define SPC5_LINFLEX1_ERR_NUMBER 101
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#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX2 TRUE
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#define SPC5_LINFLEX2_PCTL 50
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#define SPC5_LINFLEX2_RXI_HANDLER vector119
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#define SPC5_LINFLEX2_TXI_HANDLER vector120
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#define SPC5_LINFLEX2_ERR_HANDLER vector121
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#define SPC5_LINFLEX2_RXI_NUMBER 119
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#define SPC5_LINFLEX2_TXI_NUMBER 120
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#define SPC5_LINFLEX2_ERR_NUMBER 121
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#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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#define SPC5_HAS_LINFLEX3 TRUE
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#define SPC5_LINFLEX3_PCTL 51
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#define SPC5_LINFLEX3_RXI_HANDLER vector122
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#define SPC5_LINFLEX3_TXI_HANDLER vector123
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#define SPC5_LINFLEX3_ERR_HANDLER vector124
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#define SPC5_LINFLEX3_RXI_NUMBER 122
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#define SPC5_LINFLEX3_TXI_NUMBER 123
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#define SPC5_LINFLEX3_ERR_NUMBER 124
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#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL1_CLK_DIV_VALUE)
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/* SIUL attributes.*/
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#define SPC5_HAS_SIUL TRUE
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#define SPC5_SIUL_PCTL 68
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#define SPC5_SIUL_NUM_PORTS 8
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#define SPC5_SIUL_NUM_PCRS 123
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#define SPC5_SIUL_NUM_PADSELS 32
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#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
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/* eMIOS attributes.*/
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#define SPC5_HAS_EMIOS0 TRUE
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#define SPC5_EMIOS0_PCTL 72
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#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
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#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
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#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
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#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
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#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
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#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
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#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
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#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
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#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
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#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
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#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
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#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
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#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
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#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
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#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
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#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
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#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
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#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
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#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
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#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
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#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
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#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
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#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
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#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
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#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
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#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
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#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
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#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
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#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
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SPC5_EMIOS0_GPRE_VALUE)
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#define SPC5_HAS_EMIOS1 TRUE
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#define SPC5_EMIOS1_PCTL 73
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#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
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#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
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#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
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#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
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#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
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#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
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#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
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#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
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#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
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#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
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#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
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#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
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#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
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#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
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#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
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#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
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#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
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#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
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#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
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#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
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#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
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#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
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#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
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#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
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#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
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#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
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#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
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#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
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#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
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SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
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SPC5_EMIOS1_GPRE_VALUE)
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/* FlexCAN attributes.*/
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#define SPC5_HAS_FLEXCAN0 TRUE
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#define SPC5_FLEXCAN0_PCTL 16
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#define SPC5_FLEXCAN0_MB 64
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#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
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#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
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#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
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#define SPC5_HAS_FLEXCAN1 TRUE
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#define SPC5_FLEXCAN1_PCTL 17
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#define SPC5_FLEXCAN1_MB 64
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#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
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#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
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#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
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#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
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#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
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#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
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#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
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#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
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#define SPC5_HAS_FLEXCAN2 TRUE
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#define SPC5_FLEXCAN2_PCTL 18
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#define SPC5_FLEXCAN2_MB 64
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#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
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#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
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#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
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#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
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#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
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#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
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#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
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#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
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#define SPC5_HAS_FLEXCAN3 TRUE
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#define SPC5_FLEXCAN3_PCTL 19
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#define SPC5_FLEXCAN3_MB 64
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#define SPC5_FLEXCAN3_SHARED_IRQ TRUE
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#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
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#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
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#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
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#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
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#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
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#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
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#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
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#define SPC5_HAS_FLEXCAN4 TRUE
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#define SPC5_FLEXCAN4_PCTL 20
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#define SPC5_FLEXCAN4_MB 64
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#define SPC5_FLEXCAN4_SHARED_IRQ TRUE
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#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
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#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
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#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
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#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
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#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
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#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
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#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
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#define SPC5_HAS_FLEXCAN5 TRUE
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#define SPC5_FLEXCAN5_PCTL 21
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#define SPC5_FLEXCAN5_MB 64
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#define SPC5_FLEXCAN5_SHARED_IRQ TRUE
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#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
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#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
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#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
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#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
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#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
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#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
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#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
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/** @} */
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#endif /* _SPC560BC_REGISTRY_H_ */
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/** @} */
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