416 lines
12 KiB
C
416 lines
12 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/DACv1/dac_lld.h
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* @brief STM32 DAC subsystem low level driver header.
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*
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* @addtogroup DAC
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* @{
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*/
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#ifndef _DAC_LLD_H_
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#define _DAC_LLD_H_
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#include "stm32_tim.h"
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#if HAL_USE_DAC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define STM32_DAC_CR_EN DAC_CR_EN1
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#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1
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#define STM32_DAC_CR_TEN DAC_CR_TEN1
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#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE
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#define STM32_DAC_CR_BOFF_ENABLE (uint32_t)0x00000000
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#define STM32_DAC_CR_BOFF_DISABLE DAC_CR_BOFF1
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#define STM32_DAC_CR_TSEL_NONE (uint32_t)0x00000000
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#define STM32_DAC_CR_TSEL_TIM2 DAC_CR_TEN1 | DAC_CR_TSEL1_2
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#define STM32_DAC_CR_TSEL_TIM4 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2
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#define STM32_DAC_CR_TSEL_TIM5 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1
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#define STM32_DAC_CR_TSEL_TIM6 DAC_CR_TEN1
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#define STM32_DAC_CR_TSEL_TIM7 DAC_CR_TEN1 | DAC_CR_TSEL1_1
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#define STM32_DAC_CR_TSEL_TIM3 DAC_CR_TEN1 | DAC_CR_TSEL1_0
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#define STM32_DAC_CR_TSEL_TIM18 DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1
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#define STM32_DAC_CR_TSEL_EXT_IT9 DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2
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#define STM32_DAC_CR_TSEL_SOFT DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2
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#define STM32_DAC_CR_WAVE_NONE (uint32_t)0x00000000
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#define STM32_DAC_CR_WAVE_NOISE DAC_CR_WAVE1_0
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#define STM32_DAC_CR_WAVE_TRIANGLE DAC_CR_WAVE1_1
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#define STM32_DAC_MAMP_1 (uint32_t)0x00000000
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#define STM32_DAC_MAMP_3 DAC_CR_MAMP1_0
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#define STM32_DAC_MAMP_7 DAC_CR_MAMP1_1
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#define STM32_DAC_MAMP_15 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1
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#define STM32_DAC_MAMP_31 DAC_CR_MAMP1_2
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#define STM32_DAC_MAMP_63 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2
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#define STM32_DAC_MAMP_127 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
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#define STM32_DAC_MAMP_255 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
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#define STM32_DAC_MAMP_511 DAC_CR_MAMP1_3
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#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3
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#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3
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#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief DAC CHN1 driver enable switch.
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* @details If set to @p TRUE the support for DAC CHN1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_DAC_USE_CHN1) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_CHN1 FALSE
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#endif
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/**
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* @brief DAC CHN2 driver enable switch.
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* @details If set to @p TRUE the support for DAC CHN2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_DAC_USE_CHN2) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_CHN2 FALSE
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#endif
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/**
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* @brief DAC CHN3 driver enable switch.
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* @details If set to @p TRUE the support for DAC CHN3 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_DAC_USE_CHN3) || defined(__DOXYGEN__)
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#define STM32_DAC_USE_CHN3 FALSE
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#endif
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/**
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* @brief DAC CHN1 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC_CHN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC CHN2 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC_CHN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC CHN3 interrupt priority level setting.
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*/
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#if !defined(STM32_DAC_CHN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN3_IRQ_PRIORITY 10
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#endif
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/**
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* @brief DAC CHN1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC_CHN1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN1_DMA_PRIORITY 2
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#endif
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/**
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* @brief DAC CHN2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC_CHN2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN2_DMA_PRIORITY 2
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#endif
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/**
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* @brief DAC CHN3 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_DAC_CHN3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN2_DMA_PRIORITY 2
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#endif
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/**
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* @brief DAC DMA error hook.
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*/
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#if !defined(STM32_DAC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_DAC_DMA_ERROR_HOOK(dacp) osalSysHalt()
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#endif
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/**
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* @brief DMA stream used for DAC CHN1 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#endif
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/**
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* @brief DMA stream used for DAC CHN2 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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/**
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* @brief DMA stream used for DAC CHN3 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_DAC_CHN3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1
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#error "DAC CHN1 not present in the selected device"
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#endif
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#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2
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#error "DAC CHN2 not present in the selected device"
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#endif
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#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3
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#error "DAC CHN3 not present in the selected device"
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#endif
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#if !STM32_DAC_USE_CHN1 && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3
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#error "DAC driver activated but no DAC peripheral assigned"
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#endif
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/* The following checks are only required when there is a DMA able to
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reassign streams to different channels.*/
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#if STM32_ADVANCED_DMA
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/* Check on the presence of the DMA streams settings in mcuconf.h.*/
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#if STM32_DAC_USE_CHN1 && !defined(STM32_DAC_CHN1_DMA_STREAM)
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#error "DAC1 CHN1 DMA stream not defined"
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#endif
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#if STM32_DAC_USE_CHN2 && !defined(STM32_DAC_CHN2_DMA_STREAM)
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#error "DAC1 CHN2 DMA stream not defined"
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#endif
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#if STM32_DAC_USE_CHN3 && !defined(STM32_DAC_CHN3_DMA_STREAM)
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#error "DAC1 CHN3 DMA stream not defined"
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#endif
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/* Check on the validity of the assigned DMA channels.*/
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#if STM32_DAC_USE_CHN1 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)
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#error "invalid DMA stream associated to DAC CHN1"
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#endif
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#if STM32_DAC_USE_CHN2 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)
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#error "invalid DMA stream associated to DAC CHN2"
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#endif
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#if STM32_DAC_USE_CHN3 && \
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!STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)
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#error "invalid DMA stream associated to DAC CHN3"
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#endif
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#endif /* STM32_ADVANCED_DMA */
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type of a structure representing an DAC driver.
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*/
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typedef struct DACDriver DACDriver;
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/**
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* @brief Type representing a DAC sample.
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*/
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typedef uint16_t dacsample_t;
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/**
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* @brief DAC notification callback type.
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*
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* @param[in] dacp pointer to the @p DACDriver object triggering the
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* callback
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*/
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typedef void (*daccallback_t)(DACDriver *dacp);
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typedef enum {
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DAC_DHRM_12BIT_RIGHT = 0,
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DAC_DHRM_12BIT_LEFT = 1,
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DAC_DHRM_8BIT_RIGHT = 2,
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#if STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)
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DAC_DHRM_12BIT_RIGHT_DUAL = 3,
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DAC_DHRM_12BIT_LEFT_DUAL = 4,
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DAC_DHRM_8BIT_RIGHT_DUAL = 5
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#endif
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} dacdhrmode_t;
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/**
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* @brief DAC Conversion group structure.
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*/
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typedef struct {
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/**
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* @brief Number of DAC channels.
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*/
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uint32_t num_channels;
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/**
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* @brief Operation complete callback or @p NULL.
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*/
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daccallback_t end_cb;
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/**
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* @brief Error handling callback or @p NULL.
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*/
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daccallback_t error_cb;
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} DACConversionGroup;
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief Timer frequency in Hz.
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*/
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uint32_t frequency;
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/* End of the mandatory fields.*/
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/**
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* @brief DAC data holding register mode.
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*/
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dacdhrmode_t dhrm;
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/**
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* @brief DAC initialization data.
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*/
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uint32_t cr_flags;
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} DACConfig;
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/**
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* @brief Structure representing a DAC driver.
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*/
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struct DACDriver {
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/**
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* @brief Driver state.
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*/
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dacstate_t state;
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/**
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* @brief Conversion group.
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*/
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const DACConversionGroup *grpp;
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/**
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* @brief Samples buffer pointer.
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*/
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const dacsample_t *samples;
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/**
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* @brief Samples buffer size.
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*/
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uint16_t depth;
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/**
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* @brief Current configuration data.
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*/
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const DACConfig *config;
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#if DAC_USE_WAIT || defined(__DOXYGEN__)
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/**
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* @brief Waiting thread.
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*/
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thread_reference_t thread;
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#endif /* DAC_USE_WAIT */
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#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the bus.
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*/
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mutex_t mutex;
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#endif /* DAC_USE_MUTUAL_EXCLUSION */
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#if defined(DAC_DRIVER_EXT_FIELDS)
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DAC_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the DAC registers block.
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*/
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DAC_TypeDef *dac;
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/**
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* @brief Pointer to the TIMx registers block.
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*/
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stm32_tim_t *tim;
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/**
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* @brief The Timer IRQ priority.
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*/
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uint32_t irqprio;
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/**
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* @brief Transmit DMA stream.
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*/
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const stm32_dma_stream_t *dma;
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/**
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* @brief TX DMA mode bit mask.
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*/
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uint32_t dmamode;
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/**
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* @brief Timer base clock.
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*/
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uint32_t clock;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)
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extern DACDriver DACD1;
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#endif
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#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)
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extern DACDriver DACD2;
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#endif
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#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)
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extern DACDriver DACD3;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dac_lld_init(void);
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void dac_lld_start(DACDriver *dacp);
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void dac_lld_stop(DACDriver *dacp);
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void dac_lld_start_conversion(DACDriver *dacp);
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void dac_lld_stop_conversion(DACDriver *dacp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_DAC */
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#endif /* _DAC_LLD_H_ */
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/** @} */
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