310 lines
14 KiB
C
310 lines
14 KiB
C
/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC560Pxx/spc560p_registry.h
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* @brief SPC560Pxx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _SPC560P_REGISTRY_H_
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#define _SPC560P_REGISTRY_H_
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if defined(_SPC560P34L1_) || defined(_SPC560P34L3_)
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#define _SPC560P34_
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#define _SPC560PXX_SMALL_
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#elif defined(_SPC560P40L1_) || defined(_SPC560P40L3_)
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#define _SPC560P40_
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#define _SPC560PXX_SMALL_
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#elif defined(_SPC560P44L3_) || defined(_SPC560P44L5_)
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#define _SPC560P44_
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#define _SPC560PXX_MEDIUM_
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#elif defined(_SPC560P50L3_) || defined(_SPC560P50L5_)
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#define _SPC560P50_
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#define _SPC560PXX_MEDIUM_
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#elif defined(_SPC560P54L5_) || defined(_SPC56AP54L3_) || defined(_SPC56AP54L5_)
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#define _SPC560P54_
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#define _SPC560PXX_LARGE_
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#elif defined(_SPC560P60L5_) || defined(_SPC56AP60L3_) || defined(_SPC56AP60L5_)
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#define _SPC560P60_
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#define _SPC560PXX_LARGE_
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#else
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#error "SPC56xPxx platform not defined"
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name SPC560Pxx capabilities
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* @{
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*/
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/* Clock attributes.*/
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#if defined(_SPC560PXX_SMALL_)
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#define SPC5_HAS_FMPLL1 FALSE
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#define SPC5_HAS_CLOCKOUT TRUE
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#define SPC5_HAS_AC0 FALSE
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#define SPC5_HAS_AC1 FALSE
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#define SPC5_HAS_AC2 FALSE
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#define SPC5_HAS_AC3 FALSE
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#elif defined(_SPC560PXX_MEDIUM_)
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#define SPC5_HAS_FMPLL1 TRUE
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#define SPC5_HAS_CLOCKOUT TRUE
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#define SPC5_HAS_AC0 TRUE
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#define SPC5_HAS_AC1 TRUE
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#define SPC5_HAS_AC2 TRUE
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#define SPC5_HAS_AC3 TRUE
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#else /* defined(_SPC560PXX_LARGE_) */
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#define SPC5_HAS_FMPLL1 FALSE
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#define SPC5_HAS_CLOCKOUT TRUE
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#define SPC5_HAS_AC0 FALSE
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#define SPC5_HAS_AC1 FALSE
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#define SPC5_HAS_AC2 FALSE
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#define SPC5_HAS_AC3 TRUE
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#endif
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/* DSPI attribures.*/
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#define SPC5_HAS_DSPI0 TRUE
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#define SPC5_HAS_DSPI1 TRUE
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#define SPC5_HAS_DSPI2 TRUE
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#define SPC5_DSPI_FIFO_DEPTH 5
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#define SPC5_DSPI0_PCTL 4
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#define SPC5_DSPI1_PCTL 5
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#define SPC5_DSPI2_PCTL 6
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#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
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#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI0_RX_DMA_DEV_ID 2
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#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
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#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI1_RX_DMA_DEV_ID 4
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#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
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#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI2_RX_DMA_DEV_ID 6
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#define SPC5_DSPI0_TFFF_HANDLER vector76
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#define SPC5_DSPI0_TFFF_NUMBER 76
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#define SPC5_DSPI1_TFFF_HANDLER vector96
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#define SPC5_DSPI1_TFFF_NUMBER 96
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#define SPC5_DSPI2_TFFF_HANDLER vector116
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#define SPC5_DSPI2_TFFF_NUMBER 116
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#define SPC5_DSPI0_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
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#define SPC5_DSPI0_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
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#define SPC5_DSPI1_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
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#define SPC5_DSPI1_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
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#define SPC5_DSPI2_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
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#define SPC5_DSPI2_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
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#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
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#define SPC5_HAS_DSPI3 TRUE
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#define SPC5_DSPI3_PCTL 7
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#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
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#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI3_RX_DMA_DEV_ID 8
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#define SPC5_DSPI3_TFFF_HANDLER vector219
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#define SPC5_DSPI3_TFFF_NUMBER 219
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#define SPC5_DSPI3_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL)
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#define SPC5_DSPI3_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL)
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#else
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#define SPC5_HAS_DSPI3 FALSE
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#endif
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#if defined(_SPC560PXX_LARGE_)
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#define SPC5_HAS_DSPI4 TRUE
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#define SPC5_DSPI4_PCTL 8
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#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
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#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
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#define SPC5_DSPI4_RX_DMA_DEV_ID 21
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#define SPC5_DSPI4_TFFF_HANDLER vector258
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#define SPC5_DSPI4_TFFF_NUMBER 258
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#define SPC5_DSPI4_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL)
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#define SPC5_DSPI4_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI4_STOP_PCTL)
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#else
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#define SPC5_HAS_DSPI4 FALSE
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#endif
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/* eDMA attributes.*/
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#define SPC5_HAS_EDMA TRUE
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#define SPC5_EDMA_NCHANNELS 16
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#define SPC5_EDMA_HAS_MUX TRUE
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/* LINFlex attributes.*/
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#define SPC5_HAS_LINFLEX0 TRUE
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#define SPC5_LINFLEX0_PCTL 48
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#define SPC5_LINFLEX0_RXI_HANDLER vector79
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#define SPC5_LINFLEX0_TXI_HANDLER vector80
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#define SPC5_LINFLEX0_ERR_HANDLER vector81
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#define SPC5_LINFLEX0_RXI_NUMBER 79
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#define SPC5_LINFLEX0_TXI_NUMBER 80
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#define SPC5_LINFLEX0_ERR_NUMBER 81
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#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / 1)
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#define SPC5_HAS_LINFLEX1 TRUE
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#define SPC5_LINFLEX1_PCTL 49
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#define SPC5_LINFLEX1_RXI_HANDLER vector99
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#define SPC5_LINFLEX1_TXI_HANDLER vector100
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#define SPC5_LINFLEX1_ERR_HANDLER vector101
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#define SPC5_LINFLEX1_RXI_NUMBER 99
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#define SPC5_LINFLEX1_TXI_NUMBER 100
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#define SPC5_LINFLEX1_ERR_NUMBER 101
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#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / 1)
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#define SPC5_HAS_LINFLEX2 FALSE
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#define SPC5_HAS_LINFLEX3 FALSE
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/* SIUL attributes.*/
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#define SPC5_HAS_SIUL TRUE
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#define SPC5_SIUL_NUM_PORTS 8
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#if defined(_SPC560PXX_SMALL_)
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#define SPC5_SIUL_NUM_PCRS 72
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#else
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#define SPC5_SIUL_NUM_PCRS 108
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#endif
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#define SPC5_SIUL_NUM_PADSELS 36
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/* FlexPWM attributes.*/
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#if defined(_SPC560PXX_SMALL_) || defined(_SPC560PXX_MEDIUM_)
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#define SPC5_HAS_FLEXPWM0 TRUE
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#define SPC5_FLEXPWM0_PCTL 41
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#define SPC5_FLEXPWM0_RF0_HANDLER vector179
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#define SPC5_FLEXPWM0_COF0_HANDLER vector180
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#define SPC5_FLEXPWM0_CAF0_HANDLER vector181
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#define SPC5_FLEXPWM0_RF1_HANDLER vector182
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#define SPC5_FLEXPWM0_COF1_HANDLER vector183
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#define SPC5_FLEXPWM0_CAF1_HANDLER vector184
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#define SPC5_FLEXPWM0_RF2_HANDLER vector185
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#define SPC5_FLEXPWM0_COF2_HANDLER vector186
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#define SPC5_FLEXPWM0_CAF2_HANDLER vector187
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#define SPC5_FLEXPWM0_RF3_HANDLER vector188
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#define SPC5_FLEXPWM0_COF3_HANDLER vector189
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#define SPC5_FLEXPWM0_CAF3_HANDLER vector190
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#define SPC5_FLEXPWM0_FFLAG_HANDLER vector191
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#define SPC5_FLEXPWM0_REF_HANDLER vector192
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#define SPC5_FLEXPWM0_RF0_NUMBER 179
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#define SPC5_FLEXPWM0_COF0_NUMBER 180
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#define SPC5_FLEXPWM0_CAF0_NUMBER 181
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#define SPC5_FLEXPWM0_RF1_NUMBER 182
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#define SPC5_FLEXPWM0_COF1_NUMBER 183
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#define SPC5_FLEXPWM0_CAF1_NUMBER 184
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#define SPC5_FLEXPWM0_RF2_NUMBER 185
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#define SPC5_FLEXPWM0_COF2_NUMBER 186
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#define SPC5_FLEXPWM0_CAF2_NUMBER 187
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#define SPC5_FLEXPWM0_RF3_NUMBER 188
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#define SPC5_FLEXPWM0_COF3_NUMBER 189
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#define SPC5_FLEXPWM0_CAF3_NUMBER 190
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#define SPC5_FLEXPWM0_FFLAG_NUMBER 191
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#define SPC5_FLEXPWM0_REF_NUMBER 192
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#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK
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#else /* defined(_SPC560PXX_LARGE_) */
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#define SPC5_HAS_FLEXPWM0 FALSE
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#endif /* defined(_SPC560PXX_LARGE_) */
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#define SPC5_HAS_FLEXPWM1 FALSE
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/* eTimer attributes.*/
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#define SPC5_HAS_ETIMER0 TRUE
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#define SPC5_ETIMER0_PCTL 38
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#define SPC5_ETIMER0_TC0IR_HANDLER vector157
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#define SPC5_ETIMER0_TC1IR_HANDLER vector158
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#define SPC5_ETIMER0_TC2IR_HANDLER vector159
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#define SPC5_ETIMER0_TC3IR_HANDLER vector160
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#define SPC5_ETIMER0_TC4IR_HANDLER vector161
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#define SPC5_ETIMER0_TC5IR_HANDLER vector162
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#define SPC5_ETIMER0_WTIF_HANDLER vector165
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#define SPC5_ETIMER0_RCF_HANDLER vector167
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#define SPC5_ETIMER0_TC0IR_NUMBER 157
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#define SPC5_ETIMER0_TC1IR_NUMBER 158
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#define SPC5_ETIMER0_TC2IR_NUMBER 159
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#define SPC5_ETIMER0_TC3IR_NUMBER 160
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#define SPC5_ETIMER0_TC4IR_NUMBER 161
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#define SPC5_ETIMER0_TC5IR_NUMBER 162
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#define SPC5_ETIMER0_WTIF_NUMBER 165
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#define SPC5_ETIMER0_RCF_NUMBER 167
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#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK
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#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
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#define SPC5_HAS_ETIMER1 TRUE
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#define SPC5_ETIMER1_PCTL 39
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#define SPC5_ETIMER1_TC0IR_HANDLER vector168
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#define SPC5_ETIMER1_TC1IR_HANDLER vector169
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#define SPC5_ETIMER1_TC2IR_HANDLER vector170
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#define SPC5_ETIMER1_TC3IR_HANDLER vector171
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#define SPC5_ETIMER1_TC4IR_HANDLER vector172
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#define SPC5_ETIMER1_TC5IR_HANDLER vector173
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#define SPC5_ETIMER1_RCF_HANDLER vector178
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#define SPC5_ETIMER1_TC0IR_NUMBER 168
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#define SPC5_ETIMER1_TC1IR_NUMBER 169
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#define SPC5_ETIMER1_TC2IR_NUMBER 170
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#define SPC5_ETIMER1_TC3IR_NUMBER 171
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#define SPC5_ETIMER1_TC4IR_NUMBER 172
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#define SPC5_ETIMER1_TC5IR_NUMBER 173
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#define SPC5_ETIMER1_RCF_NUMBER 178
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#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
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#else /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
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#define SPC5_HAS_ETIMER1 FALSE
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#endif /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
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#define SPC5_HAS_ETIMER2 FALSE
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/* FlexCAN attributes.*/
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#define SPC5_HAS_FLEXCAN0 TRUE
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#define SPC5_FLEXCAN0_PCTL 16
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#define SPC5_FLEXCAN0_MB 32
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
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#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
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#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
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#define SPC5_FLEXCAN0_ENABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL)
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#define SPC5_FLEXCAN0_DISABLE_CLOCK() \
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halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL)
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/** @} */
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#endif /* _SPC560P_REGISTRY_H_ */
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/** @} */
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