236 lines
8.6 KiB
C
236 lines
8.6 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file DMAv2/stm32_dma.h
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* @brief STM32F2xx Enhanced DMA helper driver header.
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* @note This file requires definitions from the ST STM32F2xx header file
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* stm32f2xx.h.
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*
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* @addtogroup STM32_DMA
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* @{
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*/
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#ifndef _STM32_DMA_H_
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#define _STM32_DMA_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Total number of DMA streams.
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* @note This is the total number of streams among all the DMA units.
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*/
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#define STM32_DMA_STREAMS 16
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/**
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* @brief Mask of the ISR bits passed to the DMA callback functions.
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*/
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#define STM32_DMA_ISR_MASK 0x3D
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/**
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* @name DMA streams identifiers
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* @{
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*/
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#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0])
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#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1])
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#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2])
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#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3])
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#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4])
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#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5])
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#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6])
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#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7])
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#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8])
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#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9])
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#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10])
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#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11])
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#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12])
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#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13])
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#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14])
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#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15])
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief STM32 DMA stream descriptor structure.
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*/
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typedef struct {
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uint32_t selfindex; /**< @brief Index to self in array. */
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DMA_TypeDef *dma; /**< @brief Associated DMA unit. */
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DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
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volatile uint32_t *isr; /**< @brief Associated xISR reg. */
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volatile uint32_t *ifcr; /**< @brief Associated xIFCR reg. */
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uint32_t ishift; /**< @brief Bits offset in xISR and
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xIFCR registers. */
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} stm32_dma_stream_t;
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/**
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* @brief STM32 DMA ISR function type.
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*
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* @param[in] p parameter for the registered function
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* @param[in] flags pre-shifted content of the xISR register, the bits
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* are aligned to bit zero
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*/
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typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Associates a peripheral data register to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the PAR register
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*
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* @special
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*/
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#define dmaStreamSetPeripheral(dmastp, addr) { \
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(dmastp)->stream->PAR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates a memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the M0AR register
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*
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* @special
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*/
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#define dmaStreamSetMemory0(dmastp, addr) { \
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(dmastp)->stream->M0AR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates an alternate memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the M1AR register
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*
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* @special
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*/
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#define dmaStreamSetMemory1(dmastp, addr) { \
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(dmastp)->stream->M1AR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates an alternate memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] size value to be written in the NDTR register
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*
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* @special
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*/
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#define dmaStreamSetTransactionSize(dmastp, size) { \
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(dmastp)->stream->NDTR = (uint32_t)(size); \
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}
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/**
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* @brief Programs the stream mode settings.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] mode1 value to be written in the FCR register
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* @param[in] mode2 value to be written in the CR register
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*
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* @special
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*/
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#define dmaStreamSetMode(dmastp, mode1, mode2) { \
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(dmastp)->stream->FCR = (uint32_t)(mode1); \
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(dmastp)->stream->CR = (uint32_t)(mode2); \
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}
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/**
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* @brief DMA stream enable.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmachp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamEnable(dmachp) { \
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(dmastp)->stream->CR |= DMA_SxCR_EN; \
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}
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/**
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* @brief DMA stream disable.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamDisable(dmastp) { \
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(dmastp)->stream->CR &= ~DMA_SxCR_EN; \
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}
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/**
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* @brief DMA stream interrupt sources clear.
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* @details Sets the appropriate CGIF bit into the IFCR register in order to
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* withdraw all the pending interrupt bits from the ISR register.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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*
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* @special
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*/
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#define dmaStreamClearInterrupt(dmastp) { \
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*(dmastp)->stream->ifcr = STM32_DMA_ISR_MASK << (dmastp)->stream->ishift; \
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}
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined()
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extern _stm32_dma_streams[STM32_DMA_STREAMS];
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void dmaInit(void);
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void dmaAllocate(stm32_dma_stream_t *dmastp,
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stm32_dmaisr_t func, void *param);
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void dmaRelease(stm32_dma_stream_t *dmastp);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _STM32_DMA_H_ */
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/** @} */
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