231 lines
7.4 KiB
C
231 lines
7.4 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file LPC11xx/hal_lld.h
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* @brief HAL subsystem low level driver header template.
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*
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* @addtogroup LPC11xx_HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "LPC11xx.h"
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#include "nvic.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "LPC11xx"
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#define IRCOSCCLK 12000000 /**< High speed internal clock. */
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#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */
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#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator
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clock source. */
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#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock
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source. */
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#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */
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#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */
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#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */
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#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief System PLL clock source.
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*/
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#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
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#endif
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/**
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* @brief System PLL multiplier.
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* @note The value must be in the 1..32 range and the final frequency
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* must not exceed the CCO ratings.
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*/
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#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLL_MUL 4
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#endif
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/**
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* @brief System PLL divider.
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* @note The value must be chosen between (2, 4, 8, 16).
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*/
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#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLL_DIV 4
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#endif
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/**
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* @brief System main clock source.
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*/
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#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
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#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
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#endif
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/**
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* @brief AHB clock divider.
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* @note The value must be chosen between (1...255).
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*/
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#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__)
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#define LPC11xx_SYSABHCLK_DIV 1
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#endif
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/**
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* @brief UART clock divider.
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* @note The value must be chosen between (1...255).
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*/
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#if !defined(LPC11xx_UART_PCLK_DIV) || defined(__DOXYGEN__)
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#define LPC11xx_UART_PCLK_DIV 1
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/**
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* @brief Calculated SYSOSCCTRL setting.
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*/
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#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
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#define LPC11xx_SYSOSCCTRL 0
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#else
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#define LPC11xx_SYSOSCCTRL 1
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLLCLKIN SYSOSCCLK
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#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS
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#define LPC11xx_SYSPLLCLKIN IRCOSCCLK
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#else
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#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified"
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#endif
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/**
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* @brief MSEL mask in SYSPLLCTRL register.
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*/
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#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \
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defined(__DOXYGEN__)
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#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1)
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#else
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#error "LPC11xx_SYSPLL_MUL out of range (1...32)"
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#endif
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/**
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* @brief PSEL mask in SYSPLLCTRL register.
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*/
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#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
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#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5)
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#elif LPC11xx_SYSPLL_DIV == 4
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#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5)
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#elif LPC11xx_SYSPLL_DIV == 8
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#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5)
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#elif LPC11xx_SYSPLL_DIV == 16
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#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5)
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#else
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#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)"
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#endif
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/**
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* @brief CCP frequency.
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*/
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#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL * \
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LPC11xx_SYSPLL_DIV)
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#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000)
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#error "CCO frequency out of the acceptable range (156...320)"
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#endif
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/**
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* @brief PLL output clock frequency.
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*/
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#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
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#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)
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#define LPC11xx_MAINCLK IRCOSCCLK
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#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
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#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN
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#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
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#define LPC11xx_MAINCLK WDGOSCCLK
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#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
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#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT
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#else
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#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified"
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#endif
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/**
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* @brief AHB clock.
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*/
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#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
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#if LPC11xx_SYSCLK > 50000000
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#error "AHB clock frequency out of the acceptable range (50MHz max)"
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#endif
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/**
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* @brief Flash wait states.
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*/
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#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
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#define LPC11xx_FLASHCFG_FLASHTIM 0
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#elif LPC11xx_SYSCLK <= 40000000
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#define LPC11xx_FLASHCFG_FLASHTIM 1
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#else
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#define LPC11xx_FLASHCFG_FLASHTIM 2
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#endif
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/**
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* @brief UART clock.
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*/
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#define LPC11xx_UART_PCLK (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void lpc111x_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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