110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
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*/
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//#define SYSCLK_48
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/*
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* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
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*/
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#define LSECLK 32768
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#define HSECLK 8000000
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#define HSICLK 8000000
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#define PLLPRE 1
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#ifdef SYSCLK_48
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#define PLLMUL 6
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#else
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#define PLLMUL 9
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#endif
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#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
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#define SYSCLK PLLCLK
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#define APB1CLK (SYSCLK / 2)
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#define APB2CLK (SYSCLK / 2)
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#define AHB1CLK (SYSCLK / 1)
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/*
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* Values derived from the clock settings.
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*/
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#ifdef SYSCLK_48
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS
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#define FLASHBITS 0x00000011
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#else
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS
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#define FLASHBITS 0x00000012
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#endif
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/*
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* Extra definitions for RCC_CR register (missing from the ST header file).
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*/
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#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3)
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/*
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* Extra definitions for RCC_CFGR register (missing from the ST header file).
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*/
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#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16)
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#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16)
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#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22)
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#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22)
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/*
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* IO pins assignments.
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*/
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#define GPIOA_BUTTON 0
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#define GPIOA_SPI1NSS 4
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#define GPIOB_SPI2NSS 12
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#define GPIOC_MMCWP 6
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#define GPIOC_MMCCP 7
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#define GPIOC_CANCNTL 10
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#define GPIOC_DISC 11
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#define GPIOC_LED 12
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/*
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* All inputs with pullups unless otherwise specified.
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*/
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#define VAL_GPIOACRL 0x88888884 // PA0:FI
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#define VAL_GPIOACRH 0x88888888
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#define VAL_GPIOAODR 0xFFFFFFFF
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#define VAL_GPIOBCRL 0x88883888 // PB3:PP
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#define VAL_GPIOBCRH 0x88888888
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#define VAL_GPIOBODR 0xFFFFFFFF
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#define VAL_GPIOCCRL 0x44888888 // PC6,PC7:FI
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#define VAL_GPIOCCRH 0x88833888 // PC11,PC12:PP
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#define VAL_GPIOCODR 0xFFFFFFFF
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#define VAL_GPIODCRL 0x88888844 // PD0,PD1:FI
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#define VAL_GPIODCRH 0x88888888
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#define VAL_GPIODODR 0xFFFFFFFF
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#define VAL_GPIOECRL 0x88888888
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#define VAL_GPIOECRH 0x88888888
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#define VAL_GPIOEODR 0xFFFFFFFF
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#endif /* _BOARD_H_ */
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