112 lines
4.1 KiB
C
112 lines
4.1 KiB
C
/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM8/hal_lld.c
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* @brief STM8 HAL subsystem low level driver source.
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*
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* @addtogroup STM8_HAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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*/
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const STM8GPIOConfig pal_default_config =
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{
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{
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{VAL_GPIOAODR, 0, VAL_GPIOADDR, VAL_GPIOACR1, VAL_GPIOACR2},
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{VAL_GPIOBODR, 0, VAL_GPIOBDDR, VAL_GPIOBCR1, VAL_GPIOBCR2},
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{VAL_GPIOCODR, 0, VAL_GPIOCDDR, VAL_GPIOCCR1, VAL_GPIOCCR2},
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{VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
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{VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
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{VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
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{VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
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{VAL_GPIOHODR, 0, VAL_GPIOHDDR, VAL_GPIOHCR1, VAL_GPIOHCR2},
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{VAL_GPIOIODR, 0, VAL_GPIOIDDR, VAL_GPIOICR1, VAL_GPIOICR2}
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}
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level HAL driver initialization.
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*/
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void hal_lld_init(void) {
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#if STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT
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#if STM8_CLOCK_SOURCE == CLK_SOURCE_HSI
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CLK_ICKR = 1; /* HSIEN */
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while ((CLK_ICKR & 2) == 0) /* HSIRDY */
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;
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#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI
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CLK_ICKR = 8; /* LSIEN */
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while ((CLK_ICKR & 16) == 0) /* LSIRDY */
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;
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#else /* STM8_CLOCK_SOURCE == CLK_SOURCE_HSE */
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CLK_ECKR = 1; /* HSEEN */
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while ((CLK_ECKR & 2) == 0) /* HSERDY */
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;
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#endif
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#if STM8_CLOCK_SOURCE != CLK_SOURCE_HSI
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/* Switching clock (manual switch mode).*/
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CLK_SWCR = 0;
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CLK_SWR = STM8_CLOCK_SOURCE;
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while ((CLK_SWCR & 8) == 0) /* SWIF */
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;
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CLK_SWCR = 2; /* SWEN */
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#endif
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/* Setting up clock dividers.*/
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CLK_CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0);
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/* Clocks initially all disabled.*/
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CLK_PCKENR1 = 0;
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CLK_PCKENR2 = 0;
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/* Other clock related initializations.*/
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CLK_CSSR = 0;
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CLK_CCOR = 0;
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CLK_CANCCR = 0;
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#endif /* STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT */
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}
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/** @} */
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