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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5578 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
pcirillo 2013-04-10 08:13:02 +00:00
parent fcbef84093
commit f74d313270
4 changed files with 72 additions and 36 deletions
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6
os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
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@ -71,7 +71,7 @@ PWMDriver PWMD5;
/** /**
* @brief PWMD6 driver identifier. * @brief PWMD6 driver identifier.
* @note The driver PWMD6 allocates the timer TIM4 when enabled. * @note The driver PWMD6 allocates the timer TIM6 when enabled.
*/ */
#if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__) #if SPC5_PWM_USE_SMOD5 || defined(__DOXYGEN__)
PWMDriver PWMD6; PWMDriver PWMD6;
@ -79,7 +79,7 @@ PWMDriver PWMD6;
/** /**
* @brief PWMD7 driver identifier. * @brief PWMD7 driver identifier.
* @note The driver PWMD7 allocates the timer TIM4 when enabled. * @note The driver PWMD7 allocates the timer TIM7 when enabled.
*/ */
#if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__) #if SPC5_PWM_USE_SMOD6 || defined(__DOXYGEN__)
PWMDriver PWMD7; PWMDriver PWMD7;
@ -87,7 +87,7 @@ PWMDriver PWMD7;
/** /**
* @brief PWMD8 driver identifier. * @brief PWMD8 driver identifier.
* @note The driver PWMD8 allocates the timer TIM4 when enabled. * @note The driver PWMD8 allocates the timer TIM8 when enabled.
*/ */
#if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__) #if SPC5_PWM_USE_SMOD7 || defined(__DOXYGEN__)
PWMDriver PWMD8; PWMDriver PWMD8;

26
os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.h
View File

@ -111,7 +111,7 @@
* @name Configuration options * @name Configuration options
* @{ * @{
*/ */
#if SPC5_HAS_FLEXPWM0 #if SPC5_HAS_FLEXPWM0 || defined(__DOXYGEN__)
/** /**
* @brief PWMD1 driver enable switch. * @brief PWMD1 driver enable switch.
* @details If set to @p TRUE the support for PWMD1 is included. * @details If set to @p TRUE the support for PWMD1 is included.
@ -199,10 +199,10 @@
#endif #endif
#endif #endif
#if SPC5_HAS_FLEXPWM1 #if SPC5_HAS_FLEXPWM1 || defined(__DOXYGEN__)
/** /**
* @brief PWMD5 driver enable switch. * @brief PWMD5 driver enable switch.
* @details If set to @p TRUE the support for PWMD4 is included. * @details If set to @p TRUE the support for PWMD5 is included.
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(SPC5_PWM_USE_SMOD4) || defined(__DOXYGEN__) #if !defined(SPC5_PWM_USE_SMOD4) || defined(__DOXYGEN__)
@ -211,7 +211,7 @@
/** /**
* @brief PWMD6 driver enable switch. * @brief PWMD6 driver enable switch.
* @details If set to @p TRUE the support for PWMD4 is included. * @details If set to @p TRUE the support for PWMD6 is included.
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(SPC5_PWM_USE_SMOD5) || defined(__DOXYGEN__) #if !defined(SPC5_PWM_USE_SMOD5) || defined(__DOXYGEN__)
@ -220,7 +220,7 @@
/** /**
* @brief PWMD7 driver enable switch. * @brief PWMD7 driver enable switch.
* @details If set to @p TRUE the support for PWMD4 is included. * @details If set to @p TRUE the support for PWMD7 is included.
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(SPC5_PWM_USE_SMOD6) || defined(__DOXYGEN__) #if !defined(SPC5_PWM_USE_SMOD6) || defined(__DOXYGEN__)
@ -229,7 +229,7 @@
/** /**
* @brief PWMD8 driver enable switch. * @brief PWMD8 driver enable switch.
* @details If set to @p TRUE the support for PWMD4 is included. * @details If set to @p TRUE the support for PWMD8 is included.
* @note The default is @p FALSE. * @note The default is @p FALSE.
*/ */
#if !defined(SPC5_PWM_USE_SMOD7) || defined(__DOXYGEN__) #if !defined(SPC5_PWM_USE_SMOD7) || defined(__DOXYGEN__)
@ -353,15 +353,15 @@ typedef struct {
*/ */
typedef struct { typedef struct {
/** /**
* @brief Timer clock in Hz. * @brief Timer clock in Hz.
* @note The low level can use assertions in order to catch invalid * @note The low level can use assertions in order to catch invalid
* frequency specifications. * frequency specifications.
*/ */
uint32_t frequency; uint32_t frequency;
/** /**
* @brief PWM period in ticks. * @brief PWM period in ticks.
* @note The low level can use assertions in order to catch invalid * @note The low level can use assertions in order to catch invalid
* period specifications. * period specifications.
*/ */
pwmcnt_t period; pwmcnt_t period;
/** /**
@ -394,7 +394,7 @@ struct PWMDriver {
*/ */
const PWMConfig *config; const PWMConfig *config;
/** /**
* @brief Current PWM period in ticks. * @brief Current PWM period in ticks.
*/ */
pwmcnt_t period; pwmcnt_t period;
#if defined(PWM_DRIVER_EXT_FIELDS) #if defined(PWM_DRIVER_EXT_FIELDS)

62
os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c
View File

@ -188,6 +188,12 @@ static uint32_t icu_active_submodules0;
static uint32_t icu_active_submodules1; static uint32_t icu_active_submodules1;
static uint32_t icu_active_submodules2; static uint32_t icu_active_submodules2;
/**
* @brief Width and Period registers.
*/
uint16_t width;
uint16_t period;
/*===========================================================================*/ /*===========================================================================*/
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
@ -216,7 +222,12 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
} }
else { else {
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U; icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0; if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) {
period = icup->etimer->CHANNEL[icup->smod_number].CAPT1.R;
period = icup->etimer->CHANNEL[icup->smod_number].CAPT1.R;
} else {
period = icup->etimer->CHANNEL[icup->smod_number].CAPT1.R;
}
_icu_isr_invoke_period_cb(icup); _icu_isr_invoke_period_cb(icup);
} }
} }
@ -228,6 +239,12 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
} }
else { else {
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U; icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) {
width = icup->etimer->CHANNEL[icup->smod_number].CAPT2.R;
width = icup->etimer->CHANNEL[icup->smod_number].CAPT2.R;
} else {
width = icup->etimer->CHANNEL[icup->smod_number].CAPT2.R;
}
_icu_isr_invoke_width_cb(icup); _icu_isr_invoke_width_cb(icup);
} }
} }
@ -238,11 +255,22 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
} }
if ((sr & 0x0040) != 0) { /* ICF1 */ if ((sr & 0x0040) != 0) { /* ICF1 */
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U; icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF1 = 1U;
icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0; if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C1FCNT == 2) {
period = icup->etimer->CHANNEL[icup->smod_number].CAPT1.R;
period = icup->etimer->CHANNEL[icup->smod_number].CAPT1.R;
} else {
period = icup->etimer->CHANNEL[icup->smod_number].CAPT1.R;
}
_icu_isr_invoke_period_cb(icup); _icu_isr_invoke_period_cb(icup);
} }
else if ((sr & 0x0080) != 0) { /* ICF2 */ else if ((sr & 0x0080) != 0) { /* ICF2 */
icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U; icup->etimerp->CHANNEL[icup->smod_number].STS.B.ICF2 = 1U;
if (icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.C2FCNT == 2) {
width = icup->etimer->CHANNEL[icup->smod_number].CAPT2.R;
width = icup->etimer->CHANNEL[icup->smod_number].CAPT2.R;
} else {
width = icup->etimer->CHANNEL[icup->smod_number].CAPT2.R;
}
_icu_isr_invoke_width_cb(icup); _icu_isr_invoke_width_cb(icup);
} }
} /* ICU_SKIP_FIRST_CAPTURE = FALSE */ } /* ICU_SKIP_FIRST_CAPTURE = FALSE */
@ -307,28 +335,28 @@ static void spc5_icu_smod_init(ICUDriver *icup) {
icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0U; icup->etimerp->CHANNEL[icup->smod_number].CTRL2.B.PIPS = 0U;
/* Set secondary source.*/ /* Set secondary source.*/
switch (icup->config->channel) { switch (icup->smod_number) {
case ICU_CHANNEL_1: case 0:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_0_INPUT_PIN; SPC5_ETIMER_COUNTER_0_INPUT_PIN;
break; break;
case ICU_CHANNEL_2: case 1:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_1_INPUT_PIN; SPC5_ETIMER_COUNTER_1_INPUT_PIN;
break; break;
case ICU_CHANNEL_3: case 2:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_2_INPUT_PIN; SPC5_ETIMER_COUNTER_2_INPUT_PIN;
break; break;
case ICU_CHANNEL_4: case 3:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_3_INPUT_PIN; SPC5_ETIMER_COUNTER_3_INPUT_PIN;
break; break;
case ICU_CHANNEL_5: case 4:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_4_INPUT_PIN; SPC5_ETIMER_COUNTER_4_INPUT_PIN;
break; break;
case ICU_CHANNEL_6: case 5:
icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC = icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.SECSRC =
SPC5_ETIMER_COUNTER_5_INPUT_PIN; SPC5_ETIMER_COUNTER_5_INPUT_PIN;
break; break;
@ -344,8 +372,8 @@ static void spc5_icu_smod_init(ICUDriver *icup) {
/* Direct pointers to the capture registers in order to make reading /* Direct pointers to the capture registers in order to make reading
data faster from within callbacks.*/ data faster from within callbacks.*/
icup->pccrp = &icup->etimerp->CHANNEL[icup->smod_number].CAPT1.R; icup->pccrp = .
icup->wccrp = &icup->etimerp->CHANNEL[icup->smod_number].CAPT2.R; icup->wccrp = &width;
/* Enable channel.*/ /* Enable channel.*/
icup->etimerp->ENBL.B.ENBL |= 1U << (icup->smod_number); icup->etimerp->ENBL.B.ENBL |= 1U << (icup->smod_number);
@ -761,9 +789,13 @@ CH_IRQ_HANDLER(SPC5_ETIMER2_TC5IR_HANDLER) {
*/ */
void icu_lld_init(void) { void icu_lld_init(void) {
/* Submodules initially all not in use.*/ /* Submodules initially all not in use.*/
icu_active_submodules0 = 0; icu_active_submodules0 = 0;
icu_active_submodules1 = 0; icu_active_submodules1 = 0;
icu_active_submodules2 = 0; icu_active_submodules2 = 0;
/* Reset width and period registers.*/
width = 0;
period = 0;
#if SPC5_ICU_USE_SMOD0 #if SPC5_ICU_USE_SMOD0
/* Driver initialization.*/ /* Driver initialization.*/
@ -1276,6 +1308,8 @@ void icu_lld_enable(ICUDriver *icup) {
/* Set Capture 1 and Capture 2 Mode.*/ /* Set Capture 1 and Capture 2 Mode.*/
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE =
SPC5_ETIMER_CPT1MODE_RISING_EDGE; SPC5_ETIMER_CPT1MODE_RISING_EDGE;
icup->etimerp->CHANNEL[icup->smod_number].CTRL3.B.ROC =
SPC5_ETIMER_ROC_REL_ON_CAP1;
icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE =
SPC5_ETIMER_CPT2MODE_FALLING_EDGE; SPC5_ETIMER_CPT2MODE_FALLING_EDGE;

14
os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.h
View File

@ -35,6 +35,7 @@
* @name Mode options * @name Mode options
* @{ * @{
*/ */
/** /**
* @brief Skip first capture cycle. * @brief Skip first capture cycle.
* @details If set to @p TRUE the first capture cycle is skipped. * @details If set to @p TRUE the first capture cycle is skipped.
@ -43,7 +44,7 @@
#if !defined(ICU_JUMP_FIRST_CAPTURE) || defined(__DOXYGEN__) #if !defined(ICU_JUMP_FIRST_CAPTURE) || defined(__DOXYGEN__)
#define ICU_SKIP_FIRST_CAPTURE FALSE #define ICU_SKIP_FIRST_CAPTURE FALSE
#endif #endif
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1 0x18 #define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_1 0x18
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2 0x19 #define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_2 0x19
#define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4 0x1A #define SPC5_ETIMER_IP_BUS_CLOCK_DIVIDE_BY_4 0x1A
@ -78,6 +79,11 @@
#define SPC5_ETIMER_CPT2MODE_FALLING_EDGE 1U #define SPC5_ETIMER_CPT2MODE_FALLING_EDGE 1U
#define SPC5_ETIMER_CPT2MODE_RISING_EDGE 2U #define SPC5_ETIMER_CPT2MODE_RISING_EDGE 2U
#define SPC5_ETIMER_CPT2MODE_ANY_EDGE 3U #define SPC5_ETIMER_CPT2MODE_ANY_EDGE 3U
#define SPC5_ETIMER_ROC_DO_NOT_RELOAD 0U
#define SPC5_ETIMER_ROC_REL_ON_CAP1 1U
#define SPC5_ETIMER_ROC_REL_ON_CAP2 2U
#define SPC5_ETIMER_ROC_REL_ON_CAP1_CAP2 3U
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/
@ -445,11 +451,7 @@ typedef struct {
/** /**
* @brief Callback for timer overflow. * @brief Callback for timer overflow.
*/ */
icucallback_t overflow_cb; icucallback_t overflow_cb
/**
* @brief eTimer input channel to be used.
*/
icuchannel_t channel;
/* End of the mandatory fields.*/ /* End of the mandatory fields.*/
} ICUConfig; } ICUConfig;