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Fixed an STM32 GPT driver problem. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3353 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2011-09-19 14:01:42 +00:00
parent 31a099cb10
commit f5c7e2f7cd
2 changed files with 5 additions and 1 deletions
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4
os/hal/platforms/STM32/gpt_lld.c
View File

@ -401,6 +401,10 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
gptp->tim->ARR = interval - 1; /* Time constant. */ gptp->tim->ARR = interval - 1; /* Time constant. */
gptp->tim->EGR = TIM_EGR_UG; /* Update event. */ gptp->tim->EGR = TIM_EGR_UG; /* Update event. */
gptp->tim->CNT = 0; /* Reset counter. */
/* NOTE: After generating the UG event it takes several clock cycles before
SR bit 0 goes to 1. This is because the clearing of CNT has been inserted
before the clearing of SR, to give it some time.*/
gptp->tim->SR = 0; /* Clear pending IRQs (if any). */ gptp->tim->SR = 0; /* Clear pending IRQs (if any). */
gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */ gptp->tim->DIER = TIM_DIER_UIE; /* Update Event IRQ enabled. */
gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN; gptp->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN;

2
testhal/STM32L1xx/GPT/main.c
View File

@ -29,7 +29,7 @@ static void gpt2cb(GPTDriver *gptp) {
(void)gptp; (void)gptp;
palSetPad(GPIOB, GPIOB_LED4); palSetPad(GPIOB, GPIOB_LED4);
chSysLockFromIsr(); chSysLockFromIsr();
gptStartOneShotI(&GPTD3, 200); /* 0.02 second pulse.*/ gptStartOneShotI(&GPTD3, 1000); /* 0.02 second pulse.*/
chSysUnlockFromIsr(); chSysUnlockFromIsr();
} }