git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4058 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
f153a37e01
commit
f5c1c5fdc4
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@ -231,7 +231,7 @@ int main(void) {
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/*
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* Initializes the ADC driver 1 and enable the thermal sensor.
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* The pin PC0 on the port GPIOC is programmed as analog input.
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* The pin PC1 on the port GPIOC is programmed as analog input.
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*/
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adcStart(&ADCD1, NULL);
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adcSTM32EnableTSVREFE();
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@ -204,7 +204,7 @@ typedef struct {
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*/
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#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty
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level. */
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#define GAHBCFG_TXFELVL (1U<<7) /**< non-periodic TxFIFO empty
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#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty
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level. */
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#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */
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/** @} */
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@ -218,7 +218,7 @@ typedef struct {
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#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */
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#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field
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mask. */
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#define GUSBCFG_TRDT(n) ((n##U)<<10)/**< USB Turnaround time field
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#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field
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value. */
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#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */
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#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */
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@ -227,7 +227,7 @@ typedef struct {
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transceiver Select. */
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#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration
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field mask. */
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#define GUSBCFG_TOCAL(n) ((n##U)<<0) /**< HS/FS timeout calibration
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#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration
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field value. */
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/** @} */
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@ -237,7 +237,7 @@ typedef struct {
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*/
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#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */
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#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */
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#define GRSTCTL_TXFNUM(n) ((n##U)<<6) /**< TxFIFO number field value. */
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#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */
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#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */
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#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */
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#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */
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@ -341,20 +341,20 @@ typedef struct {
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* @{
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*/
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#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */
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#define GRXSTSR_PKTSTS(n) ((n##U)<<17)/**< Packet status value. */
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#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */
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#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1)
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#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2)
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#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3)
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#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4)
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#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6)
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#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */
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#define GRXSTSR_DPID(n) ((n##U)<<15)/**< Data PID value. */
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#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */
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#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
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#define GRXSTSR_BCNT(n) ((n##U)<<4) /**< Byte count value. */
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#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */
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#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */
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#define GRXSTSR_CHNUM(n) ((n##U)<<0) /**< Channel number value. */
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#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */
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#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
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#define GRXSTSR_EPNUM(n) ((n##U)<<0) /**< Endpoint number value. */
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#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
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/** @} */
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/**
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@ -362,20 +362,20 @@ typedef struct {
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* @{
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*/
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#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */
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#define GRXSTSP_PKTSTS(n) ((n##U)<<17)/**< Packet status value. */
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#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */
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#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1)
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#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2)
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#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3)
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#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4)
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#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6)
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#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */
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#define GRXSTSP_DPID(n) ((n##U)<<15)/**< Data PID value. */
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#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */
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#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
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#define GRXSTSP_BCNT(n) ((n##U)<<4) /**< Byte count value. */
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#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */
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#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */
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#define GRXSTSP_CHNUM(n) ((n##U)<<0) /**< Channel number value. */
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#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */
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#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
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#define GRXSTSP_EPNUM(n) ((n##U)<<0) /**< Endpoint number value. */
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#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
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/** @} */
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/**
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@ -383,7 +383,7 @@ typedef struct {
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* @{
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*/
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#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */
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#define GRXFSIZ_RXFD(n) ((n##U)<<0) /**< RxFIFO depth value. */
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#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */
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/** @} */
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/**
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@ -404,11 +404,11 @@ typedef struct {
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*/
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#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO
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depth mask. */
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#define HPTXFSIZ_PTXFD(n) ((n##U)<<16)/**< Host periodic TxFIFO
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#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO
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depth value. */
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#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO
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Start address mask. */
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#define HPTXFSIZ_PTXSA(n) ((n##U)<<0) /**< Host periodic TxFIFO
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#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO
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start address value. */
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/** @} */
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@ -430,7 +430,7 @@ typedef struct {
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* @{
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*/
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#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */
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#define HFIR_FRIVL(n) ((n##U)<<0) /**< Frame interval value. */
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#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */
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/** @} */
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/**
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@ -438,9 +438,9 @@ typedef struct {
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* @{
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*/
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#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/
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#define HFNUM_FTREM(n) ((n##U)<<16)/**< Frame time Remaining value.*/
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#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/
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#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */
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#define HFNUM_FRNUM(n) ((n##U)<<0) /**< Frame number value. */
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#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */
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/** @} */
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/**
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@ -450,19 +450,19 @@ typedef struct {
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#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic
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transmit request queue
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mask. */
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#define HPTXSTS_PTXQTOP(n) ((n##U)<<24)/**< Top of the periodic
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#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic
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transmit request queue
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value. */
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#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request
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queue Space Available
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mask. */
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#define HPTXSTS_PTXQSAV(n) ((n##U)<<16)/**< Periodic transmit request
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#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request
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queue Space Available
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value. */
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#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data
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FIFO Space Available
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mask. */
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#define HPTXSTS_PTXFSAVL(n) ((n##U)<<0) /**< Periodic transmit Data
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#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data
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FIFO Space Available
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value. */
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/** @} */
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@ -472,7 +472,7 @@ typedef struct {
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* @{
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*/
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#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */
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#define HAINT_HAINT(n) ((n##U)<<0) /**< Channel interrupts value. */
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#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */
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/** @} */
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/**
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@ -481,7 +481,7 @@ typedef struct {
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*/
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#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask
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mask. */
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#define HAINTMSK_HAINTM(n) ((n##U)<<0) /**< Channel interrupt mask
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#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask
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value. */
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/** @} */
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@ -493,7 +493,7 @@ typedef struct {
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#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */
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#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */
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#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */
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#define HPRT_PTCTL(n) ((n##U)<<13)/**< Port Test control value. */
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#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */
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#define HPRT_PPWR (1U<<12) /**< Port power. */
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#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */
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#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */
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@ -517,11 +517,11 @@ typedef struct {
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#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */
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#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */
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#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */
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#define HCCHAR_DAD(n) ((n##U)<<22)/**< Device Address value. */
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#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */
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#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */
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#define HCCHAR_MCNT(n) ((n##U)<<20)/**< Multicount value. */
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#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */
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#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
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#define HCCHAR_EPTYP(n) ((n##U)<<18)/**< Endpoint type value. */
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#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */
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#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */
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#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/
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#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */
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@ -529,7 +529,7 @@ typedef struct {
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#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */
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#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */
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#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */
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#define HCCHAR_EPNUM(n) ((n##U)<<11)/**< Endpoint number value. */
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#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */
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#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */
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#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */
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/** @} */
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@ -584,9 +584,9 @@ typedef struct {
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#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */
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#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */
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#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
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#define HCTSIZ_PKTCNT(n) ((n##U)<<19)/**< Packet count value. */
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#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
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#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */
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#define HCTSIZ_XFRSIZ(n) ((n##U)<<0) /**< Transfer size value. */
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#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
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/** @} */
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/**
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@ -595,10 +595,10 @@ typedef struct {
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*/
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#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval
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mask. */
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#define DCFG_PFIVL(n) ((n##U)<<11)/**< Periodic frame interval
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value. */
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#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval
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value. */
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#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */
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#define DCFG_DAD(n) ((n##U)<<4) /**< Device address value. */
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#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */
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#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status
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OUT handshake. */
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#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */
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@ -619,7 +619,7 @@ typedef struct {
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#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic
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IN NAK. */
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#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */
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#define DCTL_TCTL(n) ((n##U)<<4 /**< Test control value. */
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#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */
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#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */
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#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN
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NAK status. */
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*/
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#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received
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SOF mask. */
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#define DSTS_FNSOF(n) ((n##U)<<8) /**< Frame number of the received
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#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received
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SOF value. */
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#define DSTS_EERR (1U<<3) /**< Erratic error. */
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#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */
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@ -678,11 +678,11 @@ typedef struct {
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*/
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#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt
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bits mask. */
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#define DAINT_OEPINT(n) ((n##U)<<16)/**< OUT endpoint interrupt
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#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt
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bits value. */
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#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt
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bits mask. */
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#define DAINT_IEPINT(n) ((n##U)<<0) /**< IN endpoint interrupt
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#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt
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bits value. */
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/** @} */
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@ -706,7 +706,7 @@ typedef struct {
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*/
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#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge
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time mask. */
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#define DVBUSDIS_VBUSDT(n) ((n##U)<<0) /**< Device VBUS discharge
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#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge
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time value. */
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/** @} */
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@ -716,7 +716,7 @@ typedef struct {
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*/
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#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time
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mask. */
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#define DVBUSPULSE_DVBUSP(n) ((n##U)<<0) /**< Device VBUS pulsing time
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#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time
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value. */
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/** @} */
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@ -741,7 +741,7 @@ typedef struct {
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#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
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#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
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#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */
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#define DIEPCTL_TXFNUM(n) ((n##U)<<22)/**< TxFIFO number value. */
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#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */
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#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */
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#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */
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#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */
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@ -754,7 +754,7 @@ typedef struct {
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#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
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#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
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#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
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#define DIEPCTL_MPSIZ(n) ((n##U)<<0) /**< Maximum Packet size value. */
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#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
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/** @} */
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/**
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@ -776,11 +776,11 @@ typedef struct {
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* @{
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*/
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#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */
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#define DIEPTSIZ_MCNT(n) ((n##U)<<29)/**< Multi count value. */
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#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */
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#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */
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#define DIEPTSIZ_PKTCNT(n) ((n##U)<<19)/**< Packet count value. */
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||||
#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
|
||||
#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
|
||||
#define DIEPTSIZ_XFRSIZ(n) ((n##U)<<0) /**< Transfer size value. */
|
||||
#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -807,7 +807,7 @@ typedef struct {
|
|||
#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
|
||||
#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
|
||||
#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
|
||||
#define DOEPCTL_MPSIZ(n) ((n##U)<<0) /**< Maximum Packet size value. */
|
||||
#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -830,11 +830,11 @@ typedef struct {
|
|||
* @{
|
||||
*/
|
||||
#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */
|
||||
#define DOEPTSIZ_RXDPID(n) ((n##U)<<29)/**< Received data PID value. */
|
||||
#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */
|
||||
#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
|
||||
#define DOEPTSIZ_PKTCNT(n) ((n##U)<<19)/**< Packet count value. */
|
||||
#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
|
||||
#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
|
||||
#define DOEPTSIZ_XFRSIZ(n) ((n##U)<<0) /**< Transfer size value. */
|
||||
#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -33,6 +33,12 @@
|
|||
|
||||
#if HAL_USE_USB || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#define TRDT_VALUE 5
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -146,15 +152,57 @@ void usb_lld_start(USBDriver *usbp) {
|
|||
/* Clock activation.*/
|
||||
#if STM32_USB_USE_OTG1
|
||||
if (&USBD1 == usbp) {
|
||||
/* USB clock enabled.*/
|
||||
/* OTG FS clock enable and reset.*/
|
||||
rccEnableOTG1(FALSE);
|
||||
rccResetOTG1();
|
||||
|
||||
/* Enables IRQ vector.*/
|
||||
nvicEnableVector(OTG_FS_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY));
|
||||
}
|
||||
#endif
|
||||
/* Reset procedure enforced on driver start.*/
|
||||
_usb_reset(usbp);
|
||||
|
||||
/* Wait AHB idle condition.*/
|
||||
while ((OTG->GRSTCTL & GRSTCTL_AHBIDL) == 0)
|
||||
;
|
||||
|
||||
/* Core reset and delay of at least 3 PHY cycles.*/
|
||||
OTG->GRSTCTL = GRSTCTL_CSRST;
|
||||
while ((OTG->GRSTCTL & GRSTCTL_CSRST) != 0)
|
||||
;
|
||||
halPolledDelay(12);
|
||||
|
||||
/* - Forced device mode.
|
||||
- USB turnaroudn time = TRDT_VALUE.
|
||||
- Full Speed 1.1 PHY.*/
|
||||
OTG->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL;
|
||||
|
||||
/* Interrupt on TXFIFOs empty.*/
|
||||
OTG->GAHBCFG = GAHBCFG_PTXFELVL | GAHBCFG_TXFELVL;
|
||||
|
||||
/* 48MHz 1.1 PHY.*/
|
||||
OTG->DCFG = 0x02200000 | DCFG_PFIVL(0) | DCFG_DSPD_FS11;
|
||||
|
||||
/* PHY enabled.*/
|
||||
OTG->PCGCCTL = 0;
|
||||
|
||||
/* Receive FIFO size initialization, the address is always zero.*/
|
||||
OTG->GRXFSIZ = STM32_USB_OTG1_RX_FIFO_SIZE / 4;
|
||||
|
||||
/* EP0 TX FIFO initialization.*/
|
||||
|
||||
/* Endpoints reinitialization.*/
|
||||
|
||||
/* Clear all pending Device Interrupts, only the USB Reset interrupt
|
||||
is required initially.*/
|
||||
OTG->DIEPMSK = 0;
|
||||
OTG->DOEPMSK = 0;
|
||||
OTG->DAINTMSK = 0;
|
||||
OTG->GINTMSK = GINTMSK_USBRSTM;
|
||||
OTG->GINTSTS = 0xFFFFFFFF;
|
||||
|
||||
/* Global interrupts enable.*/
|
||||
OTG->GAHBCFG |= GAHBCFG_GINTMSK;
|
||||
}
|
||||
/* Configuration.*/
|
||||
}
|
||||
|
|
|
|||
|
|
@ -67,6 +67,14 @@
|
|||
#define STM32_USB_OTG1_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OTG1 RX shared FIFO size.
|
||||
* @note Must be a multiple of 4.
|
||||
*/
|
||||
#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -79,9 +87,21 @@
|
|||
#error "USB driver activated but no USB peripheral assigned"
|
||||
#endif
|
||||
|
||||
//#if STM32_USBCLK != 48000000
|
||||
//#error "the USB driver requires a 48MHz clock"
|
||||
//#endif
|
||||
#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
|
||||
#error "RX FIFO size must be a multiple of 4"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F4XX) || defined(STM32F2XX)
|
||||
#define STM32_USBCLK STM32_PLL48CLK
|
||||
#elif defined(STM32F10X_CL)
|
||||
#define STM32_USBCLK STM32_OTGFSCLK
|
||||
#else
|
||||
#error "unsupported STM32 platform for OTG functionality"
|
||||
#endif
|
||||
|
||||
#if STM32_USBCLK != 48000000
|
||||
#error "the USB OTG driver requires a 48MHz clock"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@
|
|||
Added an STM32 lwIP demo.
|
||||
- NEW: lwIP related code is not centralized into a single place, no need to
|
||||
duplicate the code in each application or demo.
|
||||
- CHANGE: Macros icuGetWidthI() and icuGetPeriodI() renemed to icuGetWidth()
|
||||
- CHANGE: Macros icuGetWidthI() and icuGetPeriodI() renamed to icuGetWidth()
|
||||
and icuGetPeriod().
|
||||
- CHANGE: Renamed Ethernet driver in AT91 HAL ETHD1.
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue