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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5646 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-04-29 09:42:43 +00:00
parent ac3085ebc9
commit f5a298cd4d
3 changed files with 18 additions and 13 deletions
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17
os/hal/platforms/SPC564Axx/hal_lld.c
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@ -73,20 +73,21 @@ void hal_lld_init(void) {
EBI (7): 3 EBI (7): 3
FlexRay (6): 4 */ FlexRay (6): 4 */
/* Downcounter timer initialized for system tick use, TB enabled for debug /* Decrementer timer initialized for system tick use, note, it is
and measurements.*/ initialized here because in the OSAL layer the system clock frequency
is not yet known.*/
n = SPC5_SYSCLK / CH_FREQUENCY; n = SPC5_SYSCLK / CH_FREQUENCY;
asm volatile ("li %%r3, 0 \t\n" asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */
"mtspr 284, %%r3 \t\n" /* Clear TBL register. */
"mtspr 285, %%r3 \t\n" /* Clear TBU register. */
"mtspr 22, %[n] \t\n" /* Init. DEC register. */
"mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
"li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3 \t\n" /* HID0 register. */
"lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
"mtspr 340, %%r3" /* TCR register. */ "mtspr 340, %%r3" /* TCR register. */
: : [n] "r" (n) : "r3"); : : [n] "r" (n) : "r3");
/* TB counter enabled for debug and measurements.*/
asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3" /* HID0 register. */
: : : "r3");
/* INTC initialization, software vector mode, 4 bytes vectors, starting /* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/ at priority 0.*/
INTC.MCR.R = 0; INTC.MCR.R = 0;

2
os/hal/platforms/SPC564Axx/hal_lld.h
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@ -153,7 +153,7 @@
/** /**
* @brief Flash buffer and prefetching settings. * @brief Flash buffer and prefetching settings.
* @note Please refer to the SPC563M64 reference manual about the meaning * @note Please refer to the SPC564Axx reference manual about the meaning
* of the following bits, if in doubt DO NOT MODIFY IT. * of the following bits, if in doubt DO NOT MODIFY IT.
* @note Do not specify the APC, WWSC, RWSC bits in this value because * @note Do not specify the APC, WWSC, RWSC bits in this value because
* those are calculated from the system clock and ORed with this * those are calculated from the system clock and ORed with this

12
os/hal/platforms/SPC56ELxx/hal_lld.c
View File

@ -59,17 +59,21 @@ void hal_lld_init(void) {
SPC5_CLOCK_FAILURE_HOOK(); SPC5_CLOCK_FAILURE_HOOK();
} }
/* Down-counter timer initialized for system tick use, TB enabled for debug /* Decrementer timer initialized for system tick use, note, it is
and measurements.*/ initialized here because in the OSAL layer the system clock frequency
is not yet known.*/
n = halSPCGetSystemClock() / CH_FREQUENCY; n = halSPCGetSystemClock() / CH_FREQUENCY;
asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */ asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */
"mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
"li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3 \t\n" /* HID0 register. */
"lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
"mtspr 340, %%r3" /* TCR register. */ "mtspr 340, %%r3" /* TCR register. */
: : [n] "r" (n) : "r3"); : : [n] "r" (n) : "r3");
/* TB counter enabled for debug and measurements.*/
asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */
"mtspr 1008, %%r3" /* HID0 register. */
: : : "r3");
/* INTC initialization, software vector mode, 4 bytes vectors, starting /* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/ at priority 0.*/
INTC.MCR.R = 0; INTC.MCR.R = 0;