git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@459 35acf78f-673a-0410-8e92-d51de3d6d3f4
parent
a3bb2266cf
commit
f44bd871c7
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@ -93,7 +93,8 @@ TCSRC =
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TCPPSRC =
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TCPPSRC =
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# List ASM source files here
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s
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ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \
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../../ports/ARM7-LPC214x/vectors.s
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# List all user directories here
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../test \
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UINCDIR = ../../src/include ../../src/lib ../../test \
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@ -93,7 +93,8 @@ TCSRC = ../../ports/ARM7-LPC214x/chcore.c \
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TCPPSRC = ../../src/lib/ch.cpp main.cpp
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TCPPSRC = ../../src/lib/ch.cpp main.cpp
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# List ASM source files here
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s
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ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \
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../../ports/ARM7-LPC214x/vectors.s
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# List all user directories here
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../test \
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UINCDIR = ../../src/include ../../src/lib ../../test \
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@ -58,10 +58,11 @@ static void T0IrqHandler(void) {
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}
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}
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/*
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/*
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* Hardware initialization goes here.
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* Early initialization code.
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* NOTE: Interrupts are still disabled.
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* This initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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*/
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void hwinit(void) {
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void hwinit0(void) {
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/*
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/*
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* All peripherals clock disabled by default in order to save power.
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* All peripherals clock disabled by default in order to save power.
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@ -106,6 +107,14 @@ void hwinit(void) {
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IO0SET = 0xFFFFFFFF;
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IO0SET = 0xFFFFFFFF;
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IO1DIR = VAL_FIO1DIR;
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IO1DIR = VAL_FIO1DIR;
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IO1SET = 0xFFFFFFFF;
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IO1SET = 0xFFFFFFFF;
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}
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/*
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* Late initialization code.
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* This initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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void hwinit1(void) {
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/*
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/*
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* Interrupt vectors assignment.
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* Interrupt vectors assignment.
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@ -132,4 +141,9 @@ void hwinit(void) {
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// InitSSP();
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// InitSSP();
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// InitMMC();
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// InitMMC();
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// InitBuzzer();
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// InitBuzzer();
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/*
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* ChibiOS/RT initialization.
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*/
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chSysInit();
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}
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}
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@ -48,7 +48,7 @@ SECTIONS
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.text :
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.text :
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{
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{
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_text = .;
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_text = .;
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KEEP(*(.startup))
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KEEP(*(vectors))
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*(.text)
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*(.text)
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*(.text.*);
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*(.text.*);
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*(.rodata);
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*(.rodata);
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@ -124,8 +124,8 @@ static void TimerHandler(eventid_t id) {
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}
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}
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/*
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/*
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* Entry point, the interrupts are disabled on entry.
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* Entry point, note, the main() function is already a thread in the system
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* This is the real "application".
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* on entry.
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*/
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*/
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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static const evhandler_t evhndl[] = {
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static const evhandler_t evhndl[] = {
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@ -134,8 +134,6 @@ int main(int argc, char **argv) {
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static EvTimer evt;
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static EvTimer evt;
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struct EventListener el0;
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struct EventListener el0;
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System::Init(); // ChibiOS/RT goes live here.
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evtInit(&evt, 500); // Initializes an event timer.
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evtInit(&evt, 500); // Initializes an event timer.
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evtStart(&evt); // Starts the event timer.
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evtStart(&evt); // Starts the event timer.
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chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source.
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chEvtRegister(&evt.et_es, &el0, 0); // Registers a listener on the source.
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@ -80,7 +80,8 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \
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TSRC =
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TSRC =
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# List ASM source files here
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s
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ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \
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../../ports/ARM7-LPC214x/vectors.s
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# List all user directories here
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib \
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UINCDIR = ../../src/include ../../src/lib \
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@ -80,7 +80,8 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \
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board.c main.c
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board.c main.c
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# List ASM source files here
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s
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ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \
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../../ports/ARM7-LPC214x/vectors.s
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# List all user directories here
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib \
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UINCDIR = ../../src/include ../../src/lib \
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@ -58,10 +58,11 @@ static void T0IrqHandler(void) {
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}
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}
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/*
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/*
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* Hardware initialization goes here.
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* Early initialization code.
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* NOTE: Interrupts are still disabled.
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* This initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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*/
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void hwinit(void) {
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void hwinit0(void) {
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/*
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/*
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* All peripherals clock disabled by default in order to save power.
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* All peripherals clock disabled by default in order to save power.
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@ -106,6 +107,14 @@ void hwinit(void) {
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IO0SET = 0xFFFFFFFF;
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IO0SET = 0xFFFFFFFF;
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IO1DIR = VAL_FIO1DIR;
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IO1DIR = VAL_FIO1DIR;
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IO1SET = 0xFFFFFFFF;
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IO1SET = 0xFFFFFFFF;
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}
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/*
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* Late initialization code.
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* This initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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void hwinit1(void) {
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/*
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/*
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* Interrupt vectors assignment.
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* Interrupt vectors assignment.
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@ -132,4 +141,9 @@ void hwinit(void) {
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// InitSSP();
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// InitSSP();
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// InitMMC();
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// InitMMC();
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// InitBuzzer();
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// InitBuzzer();
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/*
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* ChibiOS/RT initialization.
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*/
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chSysInit();
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}
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}
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@ -48,7 +48,7 @@ SECTIONS
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.text :
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.text :
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{
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{
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_text = .;
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_text = .;
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KEEP(*(.startup))
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KEEP(*(vectors))
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*(.text)
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*(.text)
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*(.text.*);
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*(.text.*);
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*(.rodata);
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*(.rodata);
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@ -56,16 +56,11 @@ static msg_t Thread2(void *arg) {
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}
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}
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/*
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/*
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* Entry point, the interrupts are disabled on entry.
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* Entry point, note, the main() function is already a thread in the system
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* on entry.
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*/
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*/
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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/*
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* The main() function becomes a thread here then the interrupts are
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* enabled and ChibiOS/RT goes live.
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*/
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chSysInit();
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/*
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/*
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* Creates the blinker threads.
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* Creates the blinker threads.
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*/
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*/
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@ -84,7 +84,8 @@ ASRC = ../../ports/ARM7-LPC214x/chcore.c \
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TSRC =
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TSRC =
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# List ASM source files here
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s
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ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \
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../../ports/ARM7-LPC214x/vectors.s
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# List all user directories here
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../test \
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UINCDIR = ../../src/include ../../src/lib ../../test \
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@ -84,7 +84,8 @@ TSRC = ../../ports/ARM7-LPC214x/chcore.c \
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board.c buzzer.c mmcsd.c main.c
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board.c buzzer.c mmcsd.c main.c
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# List ASM source files here
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# List ASM source files here
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ASMSRC = ../../ports/ARM7-LPC214x/crt0.s ../../ports/ARM7/chsys.s
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ASMSRC = ../../ports/ARM7/crt0.s ../../ports/ARM7/chsys.s \
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../../ports/ARM7-LPC214x/vectors.s
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# List all user directories here
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../test \
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UINCDIR = ../../src/include ../../src/lib ../../test \
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@ -58,10 +58,11 @@ static void T0IrqHandler(void) {
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}
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}
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/*
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/*
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* Hardware initialization goes here.
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* Early initialization code.
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* NOTE: Interrupts are still disabled.
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* This initialization is performed just after reset before BSS and DATA
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* segments initialization.
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*/
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*/
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void hwinit(void) {
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void hwinit0(void) {
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/*
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/*
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* All peripherals clock disabled by default in order to save power.
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* All peripherals clock disabled by default in order to save power.
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@ -106,6 +107,14 @@ void hwinit(void) {
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IO0SET = 0xFFFFFFFF;
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IO0SET = 0xFFFFFFFF;
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IO1DIR = VAL_FIO1DIR;
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IO1DIR = VAL_FIO1DIR;
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IO1SET = 0xFFFFFFFF;
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IO1SET = 0xFFFFFFFF;
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}
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/*
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* Late initialization code.
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* This initialization is performed after BSS and DATA segments initialization
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* and before invoking the main() function.
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*/
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void hwinit1(void) {
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/*
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/*
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* Interrupt vectors assignment.
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* Interrupt vectors assignment.
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@ -132,4 +141,9 @@ void hwinit(void) {
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InitSSP();
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InitSSP();
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InitMMC();
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InitMMC();
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InitBuzzer();
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InitBuzzer();
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/*
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* ChibiOS/RT initialization.
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*/
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chSysInit();
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}
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}
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@ -48,7 +48,7 @@ SECTIONS
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.text :
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.text :
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{
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{
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_text = .;
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_text = .;
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KEEP(*(.startup))
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KEEP(*(vectors))
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*(.text)
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*(.text)
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*(.text.*);
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*(.text.*);
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*(.rodata);
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*(.rodata);
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@ -109,7 +109,8 @@ static void RemoveHandler(eventid_t id) {
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}
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}
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/*
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/*
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* Entry point, the interrupts are disabled on entry.
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* Entry point, note, the main() function is already a thread in the system
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* on entry.
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*/
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*/
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int main(int argc, char **argv) {
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int main(int argc, char **argv) {
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static const evhandler_t evhndl[] = {
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static const evhandler_t evhndl[] = {
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@ -120,12 +121,6 @@ int main(int argc, char **argv) {
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static EvTimer evt;
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static EvTimer evt;
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struct EventListener el0, el1, el2;
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struct EventListener el0, el1, el2;
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/*
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* The main() function becomes a thread here then the interrupts are
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* enabled and ChibiOS/RT goes live.
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*/
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chSysInit();
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/*
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/*
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* If a button is pressed during the reset then the blinking leds threads
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* If a button is pressed during the reset then the blinking leds threads
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* are not started in order to make accurate benchmarks.
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* are not started in order to make accurate benchmarks.
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@ -1,172 +0,0 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Generic ARM startup file for ChibiOS/RT.
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*/
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.set MODE_USR, 0x10
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.set MODE_FIQ, 0x11
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.set MODE_IRQ, 0x12
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.set MODE_SVC, 0x13
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.set MODE_ABT, 0x17
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.set MODE_UND, 0x1B
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.set MODE_SYS, 0x1F
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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.section .startup
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.code 32
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.balign 4
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/*
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* System entry points.
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*/
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_start:
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ldr pc, _reset
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ldr pc, _undefined
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ldr pc, _swi
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ldr pc, _prefetch
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ldr pc, _abort
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nop
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ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */
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ldr pc, _fiq
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_reset:
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.word ResetHandler
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_undefined:
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.word UndHandler
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_swi:
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.word SwiHandler
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_prefetch:
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.word PrefetchHandler
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_abort:
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.word AbortHandler
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_fiq:
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.word FiqHandler
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.word 0
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.word 0
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/*
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* Reset handler.
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*/
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.text
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ResetHandler:
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/*
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* Stack pointers initialization.
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*/
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ldr r0, =__ram_end__
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/* Undefined */
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msr CPSR_c, #MODE_UND | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__und_stack_size__
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sub r0, r0, r1
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/* Abort */
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msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__abt_stack_size__
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sub r0, r0, r1
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/* FIQ */
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msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
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mov sp, r0
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ldr r1, =__fiq_stack_size__
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sub r0, r0, r1
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/* IRQ */
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msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
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mov sp, r0
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|
||||||
ldr r1, =__irq_stack_size__
|
|
||||||
sub r0, r0, r1
|
|
||||||
/* Supervisor */
|
|
||||||
msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
|
|
||||||
mov sp, r0
|
|
||||||
ldr r1, =__svc_stack_size__
|
|
||||||
sub r0, r0, r1
|
|
||||||
/* System */
|
|
||||||
msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
|
|
||||||
mov sp, r0
|
|
||||||
// ldr r1, =__sys_stack_size__
|
|
||||||
// sub r0, r0, r1
|
|
||||||
/*
|
|
||||||
* Data initialization.
|
|
||||||
* NOTE: It assumes that the DATA size is a multiple of 4.
|
|
||||||
*/
|
|
||||||
ldr r1, =_textdata
|
|
||||||
ldr r2, =_data
|
|
||||||
ldr r3, =_edata
|
|
||||||
dataloop:
|
|
||||||
cmp r2, r3
|
|
||||||
ldrlo r0, [r1], #4
|
|
||||||
strlo r0, [r2], #4
|
|
||||||
blo dataloop
|
|
||||||
/*
|
|
||||||
* BSS initialization.
|
|
||||||
* NOTE: It assumes that the BSS size is a multiple of 4.
|
|
||||||
*/
|
|
||||||
mov r0, #0
|
|
||||||
ldr r1, =_bss_start
|
|
||||||
ldr r2, =_bss_end
|
|
||||||
bssloop:
|
|
||||||
cmp r1, r2
|
|
||||||
strlo r0, [r1], #4
|
|
||||||
blo bssloop
|
|
||||||
/*
|
|
||||||
* Application-provided HW initialization routine.
|
|
||||||
*/
|
|
||||||
#ifndef THUMB_NO_INTERWORKING
|
|
||||||
bl hwinit
|
|
||||||
/*
|
|
||||||
* main(0, NULL).
|
|
||||||
*/
|
|
||||||
mov r0, #0
|
|
||||||
mov r1, r0
|
|
||||||
bl main
|
|
||||||
bl chSysHalt
|
|
||||||
#else
|
|
||||||
add r0, pc, #1
|
|
||||||
bx r0
|
|
||||||
.code 16
|
|
||||||
bl hwinit
|
|
||||||
mov r0, #0
|
|
||||||
mov r1, r0
|
|
||||||
bl main
|
|
||||||
bl chSysHalt
|
|
||||||
.code 32
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.weak UndHandler
|
|
||||||
.globl UndHandler
|
|
||||||
UndHandler:
|
|
||||||
|
|
||||||
.weak SwiHandler
|
|
||||||
.globl SwiHandler
|
|
||||||
SwiHandler:
|
|
||||||
|
|
||||||
.weak PrefetchHandler
|
|
||||||
.globl PrefetchHandler
|
|
||||||
PrefetchHandler:
|
|
||||||
|
|
||||||
.weak AbortHandler
|
|
||||||
.globl AbortHandler
|
|
||||||
AbortHandler:
|
|
||||||
|
|
||||||
.weak FiqHandler
|
|
||||||
.globl FiqHandler
|
|
||||||
FiqHandler:
|
|
||||||
|
|
||||||
.loop: b .loop
|
|
|
@ -0,0 +1,49 @@
|
||||||
|
/*
|
||||||
|
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
|
||||||
|
|
||||||
|
This file is part of ChibiOS/RT.
|
||||||
|
|
||||||
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section vectors
|
||||||
|
.code 32
|
||||||
|
.balign 4
|
||||||
|
/*
|
||||||
|
* System entry points.
|
||||||
|
*/
|
||||||
|
_start:
|
||||||
|
ldr pc, _reset
|
||||||
|
ldr pc, _undefined
|
||||||
|
ldr pc, _swi
|
||||||
|
ldr pc, _prefetch
|
||||||
|
ldr pc, _abort
|
||||||
|
nop
|
||||||
|
ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */
|
||||||
|
ldr pc, _fiq
|
||||||
|
|
||||||
|
_reset:
|
||||||
|
.word ResetHandler
|
||||||
|
_undefined:
|
||||||
|
.word UndHandler
|
||||||
|
_swi:
|
||||||
|
.word SwiHandler
|
||||||
|
_prefetch:
|
||||||
|
.word PrefetchHandler
|
||||||
|
_abort:
|
||||||
|
.word AbortHandler
|
||||||
|
_fiq:
|
||||||
|
.word FiqHandler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
|
@ -83,7 +83,7 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
|
||||||
projects. The new startup file implements early and late initialization
|
projects. The new startup file implements early and late initialization
|
||||||
phases as described above for the CM3 startup file.
|
phases as described above for the CM3 startup file.
|
||||||
The architecture specific vector tables are now encapsulated into the
|
The architecture specific vector tables are now encapsulated into the
|
||||||
vectors.s file.
|
vectors.s files.
|
||||||
- Modified the STM32 demo makefile to use the latest YAGARTO toolchain as
|
- Modified the STM32 demo makefile to use the latest YAGARTO toolchain as
|
||||||
default (arm-elf-gcc).
|
default (arm-elf-gcc).
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue