git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5450 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
de8293ab3c
commit
f24f61dc0e
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@ -8,7 +8,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
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@ -9,7 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F30x/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \
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@ -37,24 +37,6 @@ int debugzero = 0;
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/* Driver local definitions. */
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/*===========================================================================*/
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#define ADC1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
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#define ADC2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
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#define ADC3_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
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#define SDADC1_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_SDADC1_DMA_STREAM, STM32_SDADC1_DMA_CHN)
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#define SDADC2_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_SDADC2_DMA_STREAM, STM32_SDADC2_DMA_CHN)
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#define SDADC3_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_ADC_SDADC3_DMA_STREAM, STM32_SDADC3_DMA_CHN)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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@ -90,20 +72,20 @@ ADCDriver SDADCD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static bool_t isADCDriverForSigmaDeltaADC(ADCDriver *adcp);
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static bool_t isADCDriverForSuccApproxADC(ADCDriver *adcp);
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/**
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* @brief ADC DMA ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*
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* @notapi
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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@ -132,14 +114,13 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \
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defined(__DOXYGEN__)
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
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CH_IRQ_HANDLER(Vector88) {
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CH_IRQ_PROLOGUE();
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#if STM32_ADC_USE_ADC1
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@ -164,65 +145,76 @@ void adc_lld_init(void) {
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#if STM32_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc = ADC1;
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ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
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ADCD1.adc = ADC1;
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#if STM32_ADC_USE_SDADC
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ADCD1.sdadc = NULL;
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#endif
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ADCD1.dmastp = STM32_DMA1_STREAM1;
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ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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#endif
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/* The shared vector is initialized on driver initialization and never
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disabled.*/
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nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
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#endif
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#if STM32_ADC_USE_SDADC1
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/* Driver initialization.*/
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adcObjectInit(&SDADCD1);
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#if STM32_ADC_USE_ADC
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SDADCD1.adc = NULL;
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#endif
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SDADCD1.sdadc = SDADC1;
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SDADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC1_DMA_STREAM);
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SDADCD1.dmastp = STM32_DMA2_STREAM3;
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SDADCD1.dmamode = STM32_DMA_CR_CHSEL(SDADC1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_SDADC1_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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nvicEnableVector(SDADC1_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
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#endif
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#if STM32_ADC_USE_SDADC2
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/* Driver initialization.*/
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adcObjectInit(&SDADCD2);
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#if STM32_ADC_USE_ADC
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SDADCD2.adc = NULL;
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#endif
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SDADCD2.sdadc = SDADC2;
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SDADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC2_DMA_STREAM);
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SDADCD2.dmastp = STM32_DMA2_STREAM4;
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SDADCD2.dmamode = STM32_DMA_CR_CHSEL(SDADC2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_SDADC2_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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nvicEnableVector(SDADC2_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
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#endif
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#if STM32_ADC_USE_SDADC3
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/* Driver initialization.*/
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adcObjectInit(&SDADCD3);
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#if STM32_ADC_USE_ADC
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SDADCD3.adc = NULL;
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#endif
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SDADCD3.sdadc = SDADC3;
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SDADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_SDADC3_DMA_STREAM);
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SDADCD3.dmastp = STM32_DMA2_STREAM5;
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SDADCD3.dmamode = STM32_DMA_CR_CHSEL(SDADC3_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_ADC_SDADC3_DMA_PRIORITY) |
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STM32_DMA_CR_DIR_P2M |
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STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
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STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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nvicEnableVector(SDADC3_IRQn,
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CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
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#endif
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nvicEnableVector(SDADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));
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nvicEnableVector(SDADC2_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));
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nvicEnableVector(SDADC3_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));
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}
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#if 0
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/**
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* @brief Initial config for SDADC peripheral.
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*
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@ -289,8 +281,7 @@ void sdadc_lld_start_cr_init_helper(ADCDriver* adcdp,
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adcdp->sdadc->CR2 = 0;
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adcdp->sdadc->CR2 = SDADC_CR2_ADON;
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}
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#endif
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/**
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* @brief Configures and activates the ADC peripheral.
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@ -315,7 +306,7 @@ void adc_lld_start(ADCDriver *adcdp) {
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rccEnableADC1(FALSE);
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/* ADC initial setup, starting the analog part here in order to reduce
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the latency when starting a conversion.*/
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the latency when starting a conversion.*/
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adcdp->adc->CR1 = 0;
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adcdp->adc->CR2 = 0;
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adcdp->adc->CR2 = ADC_CR2_ADON;
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@ -329,9 +320,7 @@ void adc_lld_start(ADCDriver *adcdp) {
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(stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
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&SDADC1->RDATAR,
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RCC_APB2ENR_SDADC1EN);
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rccEnablePWRInterface(FALSE);
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PWR->CR |= PWR_CR_SDADC1EN;
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}
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#endif /* STM32_ADC_USE_SDADC1 */
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@ -342,8 +331,6 @@ void adc_lld_start(ADCDriver *adcdp) {
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(stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
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&SDADC2->RDATAR,
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RCC_APB2ENR_SDADC2EN);
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rccEnablePWRInterface(FALSE);
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PWR->CR |= PWR_CR_SDADC2EN;
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}
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#endif /* STM32_ADC_USE_SDADC2 */
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@ -355,11 +342,9 @@ void adc_lld_start(ADCDriver *adcdp) {
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(stm32_dmaisr_t) adc_lld_serve_rx_interrupt,
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&SDADC3->RDATAR,
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RCC_APB2ENR_SDADC3EN);
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rccEnablePWRInterface(FALSE);
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PWR->CR |= PWR_CR_SDADC3EN;
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}
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#endif /* STM32_ADC_USE_SDADC3 */
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}
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}
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@ -375,41 +360,42 @@ void adc_lld_stop(ADCDriver *adcdp) {
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/* If in ready state then disables the ADC clock.*/
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if (adcdp->state == ADC_READY) {
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dmaStreamRelease(adcdp->dmastp);
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adcdp->adc->CR1 = 0;
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adcdp->adc->CR2 = 0;
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#if STM32_ADC_USE_ADC1
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if (&ADCD1 == adcdp)
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if (&ADCD1 == adcdp) {
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adcdp->adc->CR1 = 0;
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adcdp->adc->CR2 = 0;
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rccDisableADC1(FALSE);
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}
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#endif
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#if STM32_ADC_USE_ADC2
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if (&ADCD2 == adcdp)
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rccDisableADC2(FALSE);
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#endif
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#if STM32_ADC_USE_ADC3
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if (&ADCD3 == adcdp)
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rccDisableADC3(FALSE);
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#endif
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}
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#if STM32_ADC_USE_SDADC1
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if (&SDADCD1 == adcdp)
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if (&SDADCD1 == adcdp) {
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adcdp->sdadc-CR1 = 0;
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adcdp->sdadc-CR2 = 0;
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rccDisableSDADC1(FALSE);
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PWR->CR &= ~PWR_CR_SDADC1EN;
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}
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#endif
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#if STM32_ADC_USE_SDADC2
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if (&SDADCD2 == adcdp)
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if (&SDADCD2 == adcdp) {
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adcdp->sdadc-CR1 = 0;
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adcdp->sdadc-CR2 = 0;
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rccDisableSDADC2(FALSE);
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PWR->CR &= ~PWR_CR_SDADC2EN;
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}
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#endif
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#if STM32_ADC_USE_SDADC3
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if (&SDADCD3 == adcdp)
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if (&SDADCD3 == adcdp) {
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adcdp->sdadc-CR1 = 0;
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adcdp->sdadc-CR2 = 0;
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rccDisableSDADC3(FALSE);
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PWR->CR &= ~PWR_CR_SDADC3EN;
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}
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#endif
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}
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}
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/**
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@ -421,7 +407,6 @@ void adc_lld_stop(ADCDriver *adcdp) {
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*/
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void adc_lld_start_conversion(ADCDriver *adcdp) {
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uint32_t mode;
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const ADCConversionGroup* grpp = adcdp->grpp;
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/* DMA setup.*/
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@ -441,27 +426,34 @@ void adc_lld_start_conversion(ADCDriver *adcdp) {
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dmaStreamSetMode(adcdp->dmastp, mode);
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dmaStreamEnable(adcdp->dmastp);
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if (isADCDriverForSuccApproxADC(adcdp)) {
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#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
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if (adcdp->adc != NULL) {
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#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
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#if STM32_ADC_USE_ADC
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/* ADC setup.*/
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adcdp->adc->SR = 0;
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adcdp->adc->SMPR1 = grpp->ll.adc.smpr1;
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adcdp->adc->SMPR2 = grpp->ll.adc.smpr2;
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adcdp->adc->SQR1 = grpp->ll.adc.sqr1;
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adcdp->adc->SQR2 = grpp->ll.adc.sqr2;
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adcdp->adc->SQR3 = grpp->ll.adc.sqr3;
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adcdp->adc->SMPR1 = grpp->u.adc.smpr[0];
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adcdp->adc->SMPR2 = grpp->u.adc.smpr[1];
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adcdp->adc->SQR1 = grpp->u.adc.sqr[0] |
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ADC_SQR1_NUM_CH(grpp->num_channels);
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adcdp->adc->SQR2 = grpp->u.adc.sqr[1];
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adcdp->adc->SQR3 = grpp->u.adc.sqr[2];
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/* ADC configuration and start, the start is performed using the method
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specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
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adcdp->adc->CR1 = grpp->ll.adc.cr1 | ADC_CR1_SCAN;
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if ((grpp->ll.adc.cr2 & ADC_CR2_SWSTART) != 0)
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adcdp->adc->CR2 = grpp->ll.adc.cr2 | ADC_CR2_CONT
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| ADC_CR2_DMA | ADC_CR2_ADON;
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adcdp->adc->CR1 = grpp->u.adc.cr1 | ADC_CR1_SCAN;
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if ((grpp->u.adc.cr2 & ADC_CR2_SWSTART) != 0)
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adcdp->adc->CR2 = grpp->u.adc.cr2 | ADC_CR2_CONT
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| ADC_CR2_DMA | ADC_CR2_ADON;
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else
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adcdp->adc->CR2 = grpp->ll.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
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adcdp->adc->CR2 = grpp->u.adc.cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
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#endif /* STM32_ADC_USE_ADC */
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#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
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}
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else if (isADCDriverForSigmaDeltaADC(adcdp)) {
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/* For Sigma-Delta ADC */
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else if (adcdp->sdadc != NULL) {
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#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
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#if STM32_ADC_USE_SDADC
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/* SDADC setup.*/
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sdadcSTM32SetInitializationMode(adcdp, true);
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/* SDADC setup.*/
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@ -477,10 +469,14 @@ void adc_lld_start_conversion(ADCDriver *adcdp) {
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specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
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adcdp->sdadc->CR1 = grpp->ll.sdadc.cr1 | SDADC_CR1_RDMAEN;
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adcdp->sdadc->CR2 = grpp->ll.sdadc.cr2 | SDADC_CR2_ADON;
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#endif /* STM32_ADC_USE_SDADC */
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#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
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}
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else {
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chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state");
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}
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#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
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}
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bool_t stopconv = FALSE;
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/**
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* @brief Stops an ongoing conversion.
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@ -490,66 +486,36 @@ bool_t stopconv = FALSE;
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* @notapi
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*/
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void adc_lld_stop_conversion(ADCDriver *adcdp) {
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/* Disabling the associated DMA stream.*/
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dmaStreamDisable(adcdp->dmastp);
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if (isADCDriverForSuccApproxADC(adcdp)) {
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#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
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if (adcdp->adc != NULL) {
|
||||
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
|
||||
#if STM32_ADC_USE_ADC
|
||||
adcdp->adc->CR1 = 0;
|
||||
adcdp->adc->CR2 = 0;
|
||||
adcdp->adc->CR2 = ADC_CR2_ADON;
|
||||
#endif /* STM32_ADC_USE_ADC */
|
||||
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
|
||||
}
|
||||
else if (isADCDriverForSigmaDeltaADC(adcdp)) {
|
||||
else if (adcdp->sdadc != NULL) {
|
||||
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
|
||||
#if STM32_ADC_USE_SDADC
|
||||
adcdp->sdadc->CR1 = 0;
|
||||
adcdp->sdadc->CR2 = 0;
|
||||
adcdp->sdadc->CR2 = ADC_CR2_ADON;
|
||||
#endif /* STM32_ADC_USE_SDADC */
|
||||
#if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC
|
||||
}
|
||||
else {
|
||||
chDbgAssert(FALSE, "adc_lld_stop_conversion(), #1", "invalid state");
|
||||
}
|
||||
#endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */
|
||||
}
|
||||
|
||||
#if 0
|
||||
/**
|
||||
* @brief Enables the TSVREFE bit.
|
||||
* @details The TSVREFE bit is required in order to sample the internal
|
||||
* temperature sensor and internal reference voltage.
|
||||
* @note This is an STM32-only functionality.
|
||||
*/
|
||||
void adcSTM32EnableTSVREFE(void) {
|
||||
|
||||
ADC->CCR |= ADC_CCR_TSVREFE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the TSVREFE bit.
|
||||
* @details The TSVREFE bit is required in order to sample the internal
|
||||
* temperature sensor and internal reference voltage.
|
||||
* @note This is an STM32-only functionality.
|
||||
*/
|
||||
void adcSTM32DisableTSVREFE(void) {
|
||||
|
||||
ADC->CCR &= ~ADC_CCR_TSVREFE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the VBATE bit.
|
||||
* @details The VBATE bit is required in order to sample the VBAT channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*/
|
||||
void adcSTM32EnableVBATE(void) {
|
||||
|
||||
ADC->CCR |= ADC_CCR_VBATE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the VBATE bit.
|
||||
* @details The VBATE bit is required in order to sample the VBAT channel.
|
||||
* @note This is an STM32-only functionality.
|
||||
* @note This function is meant to be called after @p adcStart().
|
||||
*/
|
||||
void adcSTM32DisableVBATE(void) {
|
||||
|
||||
ADC->CCR &= ~ADC_CCR_VBATE;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Sets the VREF for the 3 Sigma-Delta ADC Converters
|
||||
* @details VREF can be changed only when all SDADCs are disabled. Disables all SDADCs, sets the value and then sleeps 5 ms waiting for the change to occur.
|
||||
|
|
@ -697,14 +663,7 @@ void sdadcSTM32Calibrate(ADCDriver* adcdp,
|
|||
/* cleanup by clearing EOCALF flag */
|
||||
adcdp->sdadc->CLRISR |= SDADC_ISR_CLREOCALF;
|
||||
}
|
||||
|
||||
static bool_t isADCDriverForSigmaDeltaADC(ADCDriver *adcdp) {
|
||||
return (adcdp->sdadc != NULL);
|
||||
}
|
||||
|
||||
static bool_t isADCDriverForSuccApproxADC(ADCDriver *adcdp) {
|
||||
return (adcdp->adc != NULL);
|
||||
}
|
||||
#endif /* STM32_ADC_USE_SDADC */
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
|
|
|
|||
|
|
@ -252,6 +252,18 @@
|
|||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief At least an ADC unit is in use.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC STM32_ADC_USE_ADC1
|
||||
|
||||
/**
|
||||
* @brief At least an SDADC unit is in use.
|
||||
*/
|
||||
#define STM32_ADC_USE_SDADC (STM32_ADC_USE_SDADC1 || \
|
||||
STM32_ADC_USE_SDADC2 || \
|
||||
STM32_ADC_USE_SDADC3)
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
|
||||
#error "ADC1 not present in the selected device"
|
||||
#endif
|
||||
|
|
@ -268,8 +280,7 @@
|
|||
#error "SDADC3 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_SDADC1 && \
|
||||
!STM32_ADC_USE_SDADC2 && !STM32_ADC_USE_SDADC3
|
||||
#if !STM32_ADC_USE_ADC && !STM32_ADC_USE_SDADC
|
||||
#error "ADC driver activated but no ADC/SDADC peripheral assigned"
|
||||
#endif
|
||||
|
||||
|
|
@ -419,6 +430,7 @@ typedef struct {
|
|||
* is not NULL, then use the sdadc struct.
|
||||
*/
|
||||
union {
|
||||
#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
|
||||
struct {
|
||||
/**
|
||||
* @brief ADC CR1 register initialization data.
|
||||
|
|
@ -434,33 +446,16 @@ typedef struct {
|
|||
*/
|
||||
uint32_t cr2;
|
||||
/**
|
||||
* @brief ADC SMPR1 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 10...18.
|
||||
* @brief ADC SMPRx registers initialization data.
|
||||
*/
|
||||
uint32_t smpr1;
|
||||
uint32_t smpr[2];
|
||||
/**
|
||||
* @brief ADC SMPR2 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 0...9.
|
||||
* @brief ADC SQRx register initialization data.
|
||||
*/
|
||||
uint32_t smpr2;
|
||||
/**
|
||||
* @brief ADC SQR1 register initialization data.
|
||||
* @details Conversion group sequence 13...16 + sequence length.
|
||||
*/
|
||||
uint32_t sqr1;
|
||||
/**
|
||||
* @brief ADC SQR2 register initialization data.
|
||||
* @details Conversion group sequence 7...12.
|
||||
*/
|
||||
uint32_t sqr2;
|
||||
/**
|
||||
* @brief ADC SQR3 register initialization data.
|
||||
* @details Conversion group sequence 1...6.
|
||||
*/
|
||||
uint32_t sqr3;
|
||||
uint32_t sqr[3];
|
||||
} adc;
|
||||
#endif /* STM32_ADC_USE_ADC */
|
||||
#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
|
||||
struct {
|
||||
/**
|
||||
* @brief SDADC CR2 register initialization data.
|
||||
|
|
@ -494,6 +489,7 @@ typedef struct {
|
|||
*/
|
||||
uint32_t confchr2;
|
||||
} sdadc;
|
||||
#endif /* STM32_ADC_USE_SDADC */
|
||||
} u;
|
||||
} ADCConversionGroup;
|
||||
|
||||
|
|
@ -502,10 +498,14 @@ typedef struct {
|
|||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_ADC_USE_SDADC
|
||||
/**
|
||||
* @brief SDADC CR1 register initialization data.
|
||||
*/
|
||||
uint32_t cr1;
|
||||
#else /* !STM32_ADC_USE_SDADC */
|
||||
uint32_t dummy;
|
||||
#endif /* !STM32_ADC_USE_SDADC */
|
||||
} ADCConfig;
|
||||
|
||||
/**
|
||||
|
|
@ -553,15 +553,18 @@ struct ADCDriver {
|
|||
ADC_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
#if STM32_ADC_USE_ADC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Pointer to the ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adc;
|
||||
|
||||
#endif
|
||||
#if STM32_ADC_USE_SDADC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Pointer to the SDADCx registers block.
|
||||
*/
|
||||
SDADC_TypeDef *sdadc;
|
||||
#endif
|
||||
/**
|
||||
* @brief Pointer to associated DMA channel.
|
||||
*/
|
||||
|
|
@ -584,13 +587,10 @@ struct ADCDriver {
|
|||
* @brief Number of channels in a conversion sequence.
|
||||
*/
|
||||
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
|
||||
|
||||
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
|
||||
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
|
||||
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
|
||||
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
|
||||
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
|
||||
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
|
||||
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
|
||||
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
|
||||
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
|
||||
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
|
||||
|
||||
#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
|
||||
#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
|
||||
|
|
@ -599,10 +599,12 @@ struct ADCDriver {
|
|||
#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
|
||||
#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
|
||||
|
||||
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
|
||||
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
|
||||
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
|
||||
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
|
||||
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
|
||||
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
|
||||
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
|
||||
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
|
||||
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
|
||||
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -633,18 +635,6 @@ struct ADCDriver {
|
|||
#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Channel config settings helper macros
|
||||
* @{
|
||||
*/
|
||||
#define sdadcSTM32Channel1TO7Config(SDADC_Channel, SDADC_Conf) ((uint32_t) (SDADC_Conf << (( SDADC_Channel >> 16) << 2)))
|
||||
#define sdadcSTM32Channel8Config(SDADC_Channel, SDADC_Conf) ((uint32_t) SDADC_CONF)
|
||||
|
||||
#define sdadcSTM32ChannelSelect(SDADC_Channel) ((uint32_t) (SDADC_Channel & 0xffff0000))
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -673,14 +663,12 @@ extern "C" {
|
|||
void adc_lld_stop(ADCDriver *adcp);
|
||||
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||
void adcSTM32EnableTSVREFE(void);
|
||||
void adcSTM32DisableTSVREFE(void);
|
||||
void adcSTM32EnableVBATE(void);
|
||||
void adcSTM32DisableVBATE(void);
|
||||
#if STM32_ADC_USE_SDADC
|
||||
void sdadcSTM32SetInitializationMode(ADCDriver* adcdp, bool_t enterInitMode);
|
||||
void sdadcSTM32VREFSelect(SDADC_VREF_SEL svs);
|
||||
void sdadcSTM32Calibrate(ADCDriver* adcdp, SDADC_NUM_CALIB_SEQ numCalibSequences,
|
||||
ADCConversionGroup* grpp);
|
||||
#endif /* STM32_ADC_USE_SDADC */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F37x/stm32_dma.c \
|
|||
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c \
|
||||
|
|
|
|||
|
|
@ -368,6 +368,86 @@
|
|||
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SDADC peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the SDADC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSDADC1(lp) rccEnableAPB2(RCC_APB2ENR_SDADC1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SDADC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSDADC1(lp) rccDisableAPB2(RCC_APB2ENR_SDADC1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SDADC1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSDADC1() rccResetAPB2(RCC_APB2RSTR_SDADC1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SDADC2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSDADC2(lp) rccEnableAPB2(RCC_APB2ENR_SDADC2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SDADC2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSDADC2(lp) rccDisableAPB2(RCC_APB2ENR_SDADC2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SDADC2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSDADC2() rccResetAPB2(RCC_APB2RSTR_SDADC2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SDADC3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSDADC3(lp) rccEnableAPB2(RCC_APB2ENR_SDADC3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SDADC3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSDADC3(lp) rccDisableAPB2(RCC_APB2ENR_SDADC3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SDADC3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSDADC3() rccResetAPB2(RCC_APB2RSTR_SDADC3RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI peripherals specific RCC operations
|
||||
* @{
|
||||
|
|
|
|||
|
|
@ -61,21 +61,22 @@ static const ADCConversionGroup adcgrpcfg1 = {
|
|||
ADC_GRP1_NUM_CHANNELS,
|
||||
NULL,
|
||||
adcerrorcallback,
|
||||
0, /* CFGR */
|
||||
ADC_TR(0, 4095), /* TR1 */
|
||||
0, /* CCR */
|
||||
{ /* SMPR[2] */
|
||||
0,
|
||||
0
|
||||
},
|
||||
{ /* SQR[4] */
|
||||
ADC_SQR1_SQ1_N(ADC_CHANNEL_IN7) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN8),
|
||||
0,
|
||||
0,
|
||||
0
|
||||
.u.adc = {
|
||||
0, /* CR1 */
|
||||
0, /* CR2 */
|
||||
{ /* SMPR[2] */
|
||||
0,
|
||||
0
|
||||
},
|
||||
{ /* SQR[3] */
|
||||
0,
|
||||
0,
|
||||
0
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* ADC conversion group.
|
||||
* Mode: Continuous, 16 samples of 8 channels, SW triggered.
|
||||
|
|
@ -104,6 +105,7 @@ static const ADCConversionGroup adcgrpcfg2 = {
|
|||
0
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Red LEDs blinker thread, times are in milliseconds.
|
||||
|
|
@ -114,9 +116,9 @@ static msg_t Thread1(void *arg) {
|
|||
(void)arg;
|
||||
chRegSetThreadName("blinker");
|
||||
while (TRUE) {
|
||||
palSetPad(GPIOE, GPIOE_LED10_RED);
|
||||
palClearPad(GPIOC, GPIOC_LED1);
|
||||
chThdSleepMilliseconds(500);
|
||||
palClearPad(GPIOE, GPIOE_LED10_RED);
|
||||
palSetPad(GPIOC, GPIOC_LED1);
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -162,14 +164,14 @@ int main(void) {
|
|||
/*
|
||||
* Starts an ADC continuous conversion.
|
||||
*/
|
||||
adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
|
||||
// adcStartConversion(&ADCD1, &adcgrpcfg2, samples2, ADC_GRP2_BUF_DEPTH);
|
||||
|
||||
/*
|
||||
* Normal main() thread activity, in this demo it does nothing.
|
||||
*/
|
||||
while (TRUE) {
|
||||
if (palReadPad(GPIOA, GPIOA_BUTTON)) {
|
||||
adcStopConversion(&ADCD1);
|
||||
if (palReadPad(GPIOA, GPIOA_WKUP_BUTTON)) {
|
||||
// adcStopConversion(&ADCD1);
|
||||
}
|
||||
chThdSleepMilliseconds(500);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -67,9 +67,9 @@
|
|||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 TRUE
|
||||
#define STM32_ADC_USE_SDADC1 TRUE
|
||||
#define STM32_ADC_USE_SDADC2 TRUE
|
||||
#define STM32_ADC_USE_SDADC3 TRUE
|
||||
#define STM32_ADC_USE_SDADC1 FALSE
|
||||
#define STM32_ADC_USE_SDADC2 FALSE
|
||||
#define STM32_ADC_USE_SDADC3 FALSE
|
||||
#define STM32_ADC_SDADC_SLOW_MODE FALSE
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_SDADC1_DMA_PRIORITY 2
|
||||
|
|
|
|||
|
|
@ -8,7 +8,8 @@ The demo runs on an STMicroelectronics STM32373C-EVAL board.
|
|||
|
||||
** The Demo **
|
||||
|
||||
The application demonstrates the use of the STM32F37x ADC/SDADC driver.
|
||||
The application demonstrates the use of the STM32F37x ADC driver on the
|
||||
ADC peripheral.
|
||||
|
||||
** Board Setup **
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue