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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2997 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2011-05-22 11:51:17 +00:00
parent 2a6ece58ea
commit ee268d12c2
4 changed files with 55 additions and 15 deletions
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16
os/ports/GCC/AVR/chcore.h
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@ -36,7 +36,7 @@
* @brief If enabled allows the idle thread to enter a low power mode.
*/
#ifndef ENABLE_WFI_IDLE
#define ENABLE_WFI_IDLE 0
#define ENABLE_WFI_IDLE 0
#endif
/**
@ -47,12 +47,22 @@
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "AVR"
#define CH_ARCHITECTURE_NAME "AVR"
/**
* @brief Name of the architecture variant (optional).
*/
#define CH_CORE_VARIANT_NAME "MegaAVR"
#define CH_CORE_VARIANT_NAME "MegaAVR"
/**
* @brief Name of the compiler supported by this port.
*/
#define CH_COMPILER_NAME "GCC "__VERSION__
/**
* @brief Port-specific information string.
*/
#define CH_PORT_INFO "None"
/**
* @brief 8 bits stack and memory alignment enforcement.

16
os/ports/GCC/MSP430/chcore.h
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@ -36,7 +36,7 @@
* @brief Enables the use of a wait state in the idle thread loop.
*/
#ifndef ENABLE_WFI_IDLE
#define ENABLE_WFI_IDLE 0
#define ENABLE_WFI_IDLE 0
#endif
/**
@ -47,12 +47,22 @@
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "MSP430"
#define CH_ARCHITECTURE_NAME "MSP430"
/**
* @brief Name of the architecture variant (optional).
*/
#define CH_CORE_VARIANT_NAME "MSP430"
#define CH_CORE_VARIANT_NAME "MSP430"
/**
* @brief Name of the compiler supported by this port.
*/
#define CH_COMPILER_NAME "GCC "__VERSION__
/**
* @brief Port-specific information string.
*/
#define CH_PORT_INFO "None"
/**
* @brief 16 bits stack and memory alignment enforcement.

24
os/ports/GCC/PPC/chcore.h
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@ -37,12 +37,12 @@
* @brief Enables the use of the @p WFI instruction.
*/
#ifndef ENABLE_WFI_IDLE
#define ENABLE_WFI_IDLE 0
#define ENABLE_WFI_IDLE 0
#endif
/* Core variants identifiers.*/
#define PPC_VARIANT_e200z3 3 /**< e200z3 core identifier. */
#define PPC_VARIANT_e200z4 4 /**< e200z4 core identifier. */
#define PPC_VARIANT_e200z3 3 /**< e200z3 core identifier. */
#define PPC_VARIANT_e200z4 4 /**< e200z4 core identifier. */
/**
* @brief Core variant selector.
@ -50,7 +50,7 @@
* possibly code paths and structures into the port layer.
*/
#if !defined(PPC_VARIANT) || defined(__DOXYGEN__)
#define PPC_VARIANT PPC_VARIANT_e200z3
#define PPC_VARIANT PPC_VARIANT_e200z3
#endif
/**
@ -61,19 +61,29 @@
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "PowerPC"
#define CH_ARCHITECTURE_NAME "Power Architecture"
/**
* @brief Name of the architecture variant.
*/
#if (PPC_VARIANT == PPC_VARIANT_e200z3) || defined(__DOXYGEN__)
#define CH_CORE_VARIANT_NAME "e200z3"
#define CH_CORE_VARIANT_NAME "e200z3"
#elif PPC_VARIANT == PPC_VARIANT_e200z4
#define CH_CORE_VARIANT_NAME "e200z4"
#define CH_CORE_VARIANT_NAME "e200z4"
#else
#error "unknown or unsupported PowerPC variant specified"
#endif
/**
* @brief Name of the compiler supported by this port.
*/
#define CH_COMPILER_NAME "GCC "__VERSION__
/**
* @brief Port-specific information string.
*/
#define CH_PORT_INFO "None"
/**
* @brief Base type for stack and memory alignment.
*/

14
os/ports/GCC/SIMIA32/chcore.h
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@ -34,12 +34,22 @@
/**
* Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "Simulator"
#define CH_ARCHITECTURE_NAME "Simulator"
/**
* @brief Name of the architecture variant (optional).
*/
#define CH_CORE_VARIANT_NAME "x86 (integer only)"
#define CH_CORE_VARIANT_NAME "x86 (integer only)"
/**
* @brief Name of the compiler supported by this port.
*/
#define CH_COMPILER_NAME "GCC "__VERSION__
/**
* @brief Port-specific information string.
*/
#define CH_PORT_INFO "No preemption"
/**
* 16 bytes stack alignment.