STM32F4x. In HAL added support of power level detector.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3616 35acf78f-673a-0410-8e92-d51de3d6d3f4master
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9a98744b28
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edcb16ebeb
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@ -73,6 +73,12 @@ void hal_lld_init(void) {
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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#if STM32_PVD_ENABLE
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/* Power voltage detector initialization */
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PWR->CR |= PWR_CR_PVDE;
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PWR->CR |= STM32_PLS & STM32_PLS_MASK;
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#endif /* STM32_PVD_ENABLE */
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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@ -133,9 +133,19 @@
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* @name PWR_CR register bits definitions
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* @{
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*/
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#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
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#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
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#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
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#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
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#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
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#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
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#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
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/** @} */
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/**
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@ -538,6 +548,20 @@
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#define STM32_VOS STM32_VOS_HIGH
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#endif
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/**
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* @brief Enables or disables the power voltage detector.
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*/
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#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
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#define STM32_PVD_ENABLE FALSE
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#endif
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/**
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* @brief Enables or disables the power voltage detector.
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*/
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#if !defined(STM32_PLS) || defined(__DOXYGEN__)
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#define STM32_PLS STM32_PLS_LEV0
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#endif
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/**
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* @brief Enables or disables the HSI clock source.
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*/
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