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STM32F4x. In HAL added support of power level detector. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3616 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
barthess 2011-12-16 12:49:14 +00:00
parent 9a98744b28
commit edcb16ebeb
2 changed files with 33 additions and 3 deletions
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6
os/hal/platforms/STM32F4xx/hal_lld.c
View File

@ -73,6 +73,12 @@ void hal_lld_init(void) {
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
#if STM32_PVD_ENABLE
/* Power voltage detector initialization */
PWR->CR |= PWR_CR_PVDE;
PWR->CR |= STM32_PLS & STM32_PLS_MASK;
#endif /* STM32_PVD_ENABLE */
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif

24
os/hal/platforms/STM32F4xx/hal_lld.h
View File

@ -136,6 +136,16 @@
#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
/** @} */
/**
@ -538,6 +548,20 @@
#define STM32_VOS STM32_VOS_HIGH
#endif
/**
* @brief Enables or disables the power voltage detector.
*/
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
#define STM32_PVD_ENABLE FALSE
#endif
/**
* @brief Enables or disables the power voltage detector.
*/
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
#define STM32_PLS STM32_PLS_LEV0
#endif
/**
* @brief Enables or disables the HSI clock source.
*/