From edcb16ebebc3a72f5df73e883949255b30f64d74 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 16 Dec 2011 12:49:14 +0000
Subject: [PATCH] STM32F4x. In HAL added support of power level detector.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3616 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c |  6 ++++++
 os/hal/platforms/STM32F4xx/hal_lld.h | 30 +++++++++++++++++++++++++---
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 6922ff3df..b2862caa4 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -73,6 +73,12 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
 
+#if STM32_PVD_ENABLE
+  /* Power voltage detector initialization */
+  PWR->CR |= PWR_CR_PVDE;
+  PWR->CR |= STM32_PLS & STM32_PLS_MASK;
+#endif /* STM32_PVD_ENABLE */
+
 #if defined(STM32_DMA_REQUIRED)
   dmaInit();
 #endif
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 1aeed4755..a43268377 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -133,9 +133,19 @@
  * @name    PWR_CR register bits definitions
  * @{
  */
-#define STM32_VOS_MASK          (1 << 14)   /**< Core voltage mask.         */
-#define STM32_VOS_LOW           (0 << 14)   /**< Core voltage set to low.   */
-#define STM32_VOS_HIGH          (1 << 14)   /**< Core voltage set to high.  */
+#define STM32_VOS_MASK      (1 << 14)   /**< Core voltage mask.             */
+#define STM32_VOS_LOW       (0 << 14)   /**< Core voltage set to low.       */
+#define STM32_VOS_HIGH      (1 << 14)   /**< Core voltage set to high.      */
+
+#define STM32_PLS_MASK      (7 << 5)    /**< PLS bits mask.                 */
+#define STM32_PLS_LEV0      (0 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV1      (1 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV2      (2 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV3      (3 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV4      (4 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV5      (5 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV6      (6 << 5)    /**< PVD level 0.                   */
+#define STM32_PLS_LEV7      (7 << 5)    /**< PVD level 0.                   */
 /** @} */
 
 /**
@@ -538,6 +548,20 @@
 #define STM32_VOS                   STM32_VOS_HIGH
 #endif
 
+/**
+ * @brief   Enables or disables the power voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the power voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
 /**
  * @brief   Enables or disables the HSI clock source.
  */