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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3481 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2011-11-10 17:54:41 +00:00
parent b81fe69f71
commit ed26815f85
28 changed files with 554 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
os/hal/include/ext.h
View File

@ -81,6 +81,10 @@ typedef struct EXTDriver EXTDriver;
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Enables an EXT channel.
*
@ -100,6 +104,7 @@ typedef struct EXTDriver EXTDriver;
* @iclass
*/
#define extChannelDisableI(extp, channel) ext_lld_channel_disable(extp, channel)
/** @} */
/*===========================================================================*/
/* External declarations. */

5
os/hal/platforms/STM32/can_lld.h
View File

@ -74,6 +74,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief CAN1 driver enable switch.
* @details If set to @p TRUE the support for ADC1 is included.
@ -89,6 +93,7 @@
#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32/ext_lld.h
View File

@ -77,6 +77,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0 interrupt priority level setting.
*/
@ -174,6 +178,7 @@
#if !defined(STM32_EXT_EXTI22_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI22_IRQ_PRIORITY 6
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32/gpt_lld.h
View File

@ -39,6 +39,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief GPTD1 driver enable switch.
* @details If set to @p TRUE the support for GPTD1 is included.
@ -134,6 +138,7 @@
#if !defined(STM32_GPT_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

6
os/hal/platforms/STM32/i2c_lld.h
View File

@ -37,6 +37,11 @@
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Switch between callback based and synchronouse driver.
* @note The default is synchronouse.
@ -98,6 +103,7 @@
#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_I2C_I2C2_IRQ_PRIORITY 0xA0
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32/icu_lld.h
View File

@ -39,6 +39,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief ICUD1 driver enable switch.
* @details If set to @p TRUE the support for ICUD1 is included.
@ -134,6 +138,7 @@
#if !defined(STM32_ICU_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32/mac_lld.h
View File

@ -114,6 +114,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Number of available transmit buffers.
*/
@ -134,6 +138,7 @@
#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define MAC_BUFFERS_SIZE 1518
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32/pwm_lld.h
View File

@ -74,6 +74,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief If advanced timer features switch.
* @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
@ -179,6 +183,7 @@
#if !defined(STM32_PWM_TIM8_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#endif
/** @} */
/*===========================================================================*/
/* Configuration checks. */

5
os/hal/platforms/STM32/sdc_lld.h
View File

@ -40,6 +40,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief SDIO data timeout in SDIO clock cycles.
*/
@ -67,6 +71,7 @@
#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)
#define STM32_SDC_UNALIGNED_SUPPORT TRUE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32/serial_lld.h
View File

@ -39,6 +39,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief USART1 driver enable switch.
* @details If set to @p TRUE the support for USART1 is included.
@ -134,6 +138,7 @@
#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SERIAL_USART6_PRIORITY 12
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

173
os/hal/platforms/STM32/spi_lld.c
View File

@ -31,6 +31,34 @@
#if HAL_USE_SPI || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define SPI1_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM, \
STM32_SPI1_RX_DMA_CHN)
#define SPI1_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM, \
STM32_SPI1_TX_DMA_CHN)
#define SPI2_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM, \
STM32_SPI2_RX_DMA_CHN)
#define SPI2_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM, \
STM32_SPI2_TX_DMA_CHN)
#define SPI3_RX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM, \
STM32_SPI3_RX_DMA_CHN)
#define SPI3_TX_DMA_CHANNEL \
STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM, \
STM32_SPI3_TX_DMA_CHN)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@ -61,26 +89,6 @@ static uint16_t dummyrx;
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Stops the SPI DMA channels.
*
* @param[in] spip pointer to the @p SPIDriver object
*/
#define dma_stop(spip) { \
dmaStreamDisable(spip->dmatx); \
dmaStreamDisable(spip->dmarx); \
}
/**
* @brief Starts the SPI DMA channels.
*
* @param[in] spip pointer to the @p SPIDriver object
*/
#define dma_start(spip) { \
dmaChannelEnable((spip)->dmarx); \
dmaChannelEnable((spip)->dmatx); \
}
/**
* @brief Shared end-of-rx service routine.
*
@ -99,7 +107,8 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
#endif
/* Stop everything.*/
dma_stop(spip);
dmaStreamDisable(spip->dmatx);
dmaStreamDisable(spip->dmarx);
/* Portable SPI ISR code defined in the high level driver, note, it is
a macro.*/
@ -145,26 +154,50 @@ void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.thread = NULL;
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA1_STREAM2;
SPID1.dmatx = STM32_DMA1_STREAM3;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.thread = NULL;
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA1_STREAM4;
SPID2.dmatx = STM32_DMA1_STREAM5;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.thread = NULL;
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA2_STREAM1;
SPID3.dmatx = STM32_DMA2_STREAM2;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_TEIE;
#endif
}
@ -182,12 +215,12 @@ void spi_lld_start(SPIDriver *spip) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
bool_t b;
b = dmaStreamAllocate(STM32_DMA1_STREAM2,
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
b = dmaStreamAllocate(STM32_DMA1_STREAM3,
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
@ -198,12 +231,12 @@ void spi_lld_start(SPIDriver *spip) {
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
bool_t b;
b = dmaStreamAllocate(STM32_DMA1_STREAM4,
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
b = dmaStreamAllocate(STM32_DMA1_STREAM5,
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
@ -214,12 +247,12 @@ void spi_lld_start(SPIDriver *spip) {
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
bool_t b;
b = dmaStreamAllocate(STM32_DMA2_STREAM1,
b = dmaStreamAllocate(spip->dmarx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
b = dmaStreamAllocate(STM32_DMA2_STREAM2,
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
@ -233,18 +266,19 @@ void spi_lld_start(SPIDriver *spip) {
dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);
}
/* More DMA setup.*/
if ((spip->config->cr1 & SPI_CR1_DFF) == 0)
spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_TEIE |
STM32_DMA_CR_PSIZE_BYTE |
STM32_DMA_CR_MSIZE_BYTE; /* 8 bits transfers. */
else
spip->dmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_TEIE |
STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MSIZE_HWORD; /* 16 bits transfers. */
/* Configuration-specific DMA setup.*/
if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { /* 8 bits transfers. */
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
}
else { /* 16 bits transfers. */
spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
}
/* SPI setup and enable.*/
spip->spi->CR1 = 0;
spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM |
@ -267,27 +301,20 @@ void spi_lld_stop(SPIDriver *spip) {
/* SPI disable.*/
spip->spi->CR1 = 0;
dmaStreamRelease(spip->dmarx);
dmaStreamRelease(spip->dmatx);
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
dmaStreamRelease(STM32_DMA1_STREAM2);
dmaStreamRelease(STM32_DMA1_STREAM3);
if (&SPID1 == spip)
rccDisableSPI1(FALSE);
}
#endif
#if STM32_SPI_USE_SPI2
if (&SPID2 == spip) {
dmaStreamRelease(STM32_DMA1_STREAM4);
dmaStreamRelease(STM32_DMA1_STREAM5);
if (&SPID2 == spip)
rccDisableSPI2(FALSE);
}
#endif
#if STM32_SPI_USE_SPI3
if (&SPID3 == spip) {
dmaStreamRelease(STM32_DMA2_STREAM1);
dmaStreamRelease(STM32_DMA2_STREAM2);
if (&SPID3 == spip)
rccDisableSPI3(FALSE);
}
#endif
}
}
@ -332,12 +359,10 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);
}
/**
@ -360,13 +385,12 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC |
dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
}
/**
@ -386,12 +410,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_MINC | STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
}
/**
@ -411,13 +434,11 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
dmaStreamSetMode(spip->dmarx, spip->dmamode | STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE | STM32_DMA_CR_MINC |
dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC |
STM32_DMA_CR_EN);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
dmaStreamSetMode(spip->dmatx, spip->dmamode | STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_EN);
dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);
}
/**

136
os/hal/platforms/STM32/spi_lld.h
View File

@ -39,6 +39,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief SPI1 driver enable switch.
* @details If set to @p TRUE the support for SPI1 is included.
@ -68,9 +72,9 @@
/**
* @brief SPI1 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
@ -78,9 +82,9 @@
/**
* @brief SPI2 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_DMA_PRIORITY 1
@ -88,9 +92,9 @@
/**
* @brief SPI3 DMA priority (0..3|lowest..highest).
* @note The priority level is used for both the TX and RX DMA channels but
* because of the channels ordering the RX channel has always priority
* over the TX channel.
* @note The priority level is used for both the TX and RX DMA streams but
* because of the streams ordering the RX stream has always priority
* over the TX stream.
*/
#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_DMA_PRIORITY 1
@ -119,13 +123,64 @@
/**
* @brief SPI DMA error hook.
* @note The default action for DMA errors is a system halt because DMA
* error can only happen because programming errors.
*/
#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
#endif
#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
/**
* @brief DMA stream used for SPI1 RX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_SPI_SPI1_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#endif
/**
* @brief DMA stream used for SPI1 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_SPI_SPI1_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#endif
/**
* @brief DMA stream used for SPI2 RX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_SPI_SPI2_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#endif
/**
* @brief DMA stream used for SPI2 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_SPI_SPI2_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#endif
/**
* @brief DMA stream used for SPI3 RX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_SPI_SPI3_RX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#endif
/**
* @brief DMA stream used for SPI3 TX operations.
* @note This option is only available on platforms with enhanced DMA.
*/
#if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#endif
#endif /* STM32_ADVANCED_DMA*/
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -146,6 +201,53 @@
#error "SPI driver activated but no SPI peripheral assigned"
#endif
#if STM32_ADVANCED_DMA
/* Checks to be performed only on platforms using the advanced DMA
peripheral.*/
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 RX"
#endif
#if STM32_SPI_USE_SPI1 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI1 TX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 RX"
#endif
#if STM32_SPI_USE_SPI2 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI2 TX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 RX"
#endif
#if STM32_SPI_USE_SPI3 && \
!STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
#error "invalid DMA stream associated to SPI3 TX"
#endif
#else /* !STM32_ADVANCED_DMA */
/* Fixed streams for platforms using the old DMA peripheral, the values are
valid for both STM32F1xx and STM32L1xx.*/
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#endif /* !STM32_ADVANCED_DMA */
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
@ -227,17 +329,21 @@ struct SPIDriver{
*/
SPI_TypeDef *spi;
/**
* @brief Receive DMA channel.
* @brief Receive DMA stream.
*/
const stm32_dma_stream_t *dmarx;
/**
* @brief Transmit DMA channel.
* @brief Transmit DMA stream.
*/
const stm32_dma_stream_t *dmatx;
/**
* @brief DMA mode bit mask.
* @brief RX DMA mode bit mask.
*/
uint32_t dmamode;
uint32_t rxdmamode;
/**
* @brief TX DMA mode bit mask.
*/
uint32_t txdmamode;
};
/*===========================================================================*/

5
os/hal/platforms/STM32/uart_lld.h
View File

@ -39,6 +39,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief UART driver on USART1 enable switch.
* @details If set to @p TRUE the support for USART1 is included.
@ -124,6 +128,7 @@
#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32F1xx/adc_lld.h
View File

@ -85,6 +85,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief ADC1 driver enable switch.
* @details If set to @p TRUE the support for ADC1 is included.
@ -107,6 +111,7 @@
#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32F1xx/hal_lld_f100.h
View File

@ -337,6 +337,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
@ -423,6 +427,7 @@
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

6
os/hal/platforms/STM32F1xx/hal_lld_f103.h
View File

@ -508,6 +508,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
@ -601,6 +605,8 @@
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

5
os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
View File

@ -278,6 +278,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief PLL1 main switch.
* @note If this constant is set to @p TRUE then the PLL1 is initialized
@ -430,6 +434,7 @@
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

61
os/hal/platforms/STM32F1xx/stm32_dma.h
View File

@ -51,26 +51,56 @@
*/
#define STM32_DMA_ISR_MASK 0x0F
/**
* @brief Returns the channel associated to the specified stream.
*
* @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
* @param[in] c a stream/channel association word, one channel per
* nibble, not associated channels must be set to 0xF
* @return Always zero, in this platform there is no dynamic
* association between streams and channels.
*/
#define STM32_DMA_GETCHANNEL(n, c) 0
/**
* @name DMA streams identifiers
* @{
*/
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0])
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1])
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2])
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3])
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4])
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5])
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6])
#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[7])
#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[8])
#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[9])
#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[10])
#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[11])
/**
* @brief Returns an unique numeric identifier for a DMA stream.
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
*
* @param[in] n the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
* associated to the DMA stream.
*/
#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n])
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7)
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8)
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
/** @} */
/**
* @name CR register constants common to all DMA types
* @{
*/
#define STM32_DMA_CR_EN DMA_CCR1_EN
#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
@ -97,6 +127,7 @@
/**
* @name CR register constants only found in enhanced DMA
* @{
*/
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
@ -104,6 +135,7 @@
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
#define STM32_DMA_ISR_FEIF 0
#define STM32_DMA_ISR_DMEIF 0
@ -149,6 +181,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a peripheral data register to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
@ -302,6 +338,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
#define dmaWaitCompletion(dmastp) \
while (((dmastp)->channel->CNDTR > 0) && \
((dmastp)->channel->CCR & STM32_DMA_CR_EN))
/** @} */
/*===========================================================================*/
/* External declarations. */

50
os/hal/platforms/STM32F4xx/hal_lld.h
View File

@ -40,6 +40,10 @@
#include "stm32f4xx.h"
/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
#include "stm32_rcc.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@ -245,22 +249,30 @@
* @name STM32F4xx capabilities
* @{
*/
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
#define STM32_HAS_ADC3 TRUE
/* CAN attributes.*/
#define STM32_HAS_CAN1 TRUE
#define STM32_HAS_CAN2 TRUE
/* DAC attributes.*/
#define STM32_HAS_DAC TRUE
/* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
#define STM32_HAS_DMA1 TRUE
#define STM32_HAS_DMA2 TRUE
/* ETH attributes.*/
#define STM32_HAS_ETH TRUE
/* EXTI attributes.*/
#define STM32_EXTI_NUM_CHANNELS 23
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
@ -271,18 +283,41 @@
#define STM32_HAS_GPIOH TRUE
#define STM32_HAS_GPIOI TRUE
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
#define STM32_HAS_I2C3 TRUE
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
#define STM32_HAS_SPI2 TRUE
#define STM32_HAS_SPI3 TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000303
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SPI1_TX_DMA_CHN 0x00303000
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 TRUE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) | \
STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI3_RX_DMA_CHN 0x00000000
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) | \
STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_SPI3_TX_DMA_CHN 0x00000000
/* TIM attributes.*/
#define STM32_HAS_TIM1 TRUE
#define STM32_HAS_TIM2 TRUE
#define STM32_HAS_TIM3 TRUE
@ -301,6 +336,7 @@
#define STM32_HAS_TIM16 FALSE
#define STM32_HAS_TIM17 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_HAS_USART2 TRUE
#define STM32_HAS_USART3 TRUE
@ -308,6 +344,7 @@
#define STM32_HAS_UART5 TRUE
#define STM32_HAS_USART6 TRUE
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 TRUE
@ -415,6 +452,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
@ -620,6 +661,7 @@
#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLI2SR_VALUE 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
@ -1208,10 +1250,6 @@
/* External declarations. */
/*===========================================================================*/
/* STM32 DMA and RCC helpers.*/
#include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus
extern "C" {
#endif

4
os/hal/platforms/STM32F4xx/platform.mk
View File

@ -1,6 +1,8 @@
# List of all the STM32L1xx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F4xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
# Required include directories

4
os/hal/platforms/STM32F4xx/stm32_dma.c
View File

@ -484,8 +484,8 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
/* Putting the stream in a safe state.*/
dmaStreamDisable(dmastp);
dmaStreamClearInterrupt(dmastp);
dmastp->channel->CR = STM32_DMA_CR_RESET_VALUE;
dmastp->channel->FCR = STM32_DMA_FCR_RESET_VALUE;
dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
/* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL)

92
os/hal/platforms/STM32F4xx/stm32_dma.h
View File

@ -46,30 +46,81 @@
*/
#define STM32_DMA_ISR_MASK 0x3D
/**
* @brief Returns the channel associated to the specified stream.
*
* @param[in] id the unique numeric stream identifier
* @param[in] c a stream/channel association word, one channel per
* nibble
* @return Returns the channel associated to the stream.
*/
#define STM32_DMA_GETCHANNEL(id, c) ((c) >> (((id) & 7) * 4))
/**
* @brief Returns an unique numeric identifier for a DMA stream.
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
/**
* @brief Returns a DMA stream identifier mask.
*
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return A DMA stream identifier mask.
*/
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
(1 << STM32_DMA_STREAM_ID(dma, stream))
/**
* @brief Checks if a DMA stream unique identifier belongs to a mask.
* @param[in] id the stream numeric identifier
* @param[in] mask the stream numeric identifiers mask
*
* @retval The check result.
* @retval FALSE id does not belong to the mask.
* @retval TRUE id belongs to the mask.
*/
#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
/**
* @name DMA streams identifiers
* @{
*/
#define STM32_DMA1_STREAM0 (&_stm32_dma_streams[0])
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[1])
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[2])
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[3])
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[4])
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[5])
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[6])
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[7])
#define STM32_DMA2_STREAM0 (&_stm32_dma_streams[8])
#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[9])
#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[10])
#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[11])
#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[12])
#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[13])
#define STM32_DMA2_STREAM6 (&_stm32_dma_streams[14])
#define STM32_DMA2_STREAM7 (&_stm32_dma_streams[15])
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
*
* @param[in] id the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
* associated to the DMA stream.
*/
#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0)
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1)
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2)
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3)
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4)
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5)
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6)
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7)
#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8)
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9)
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10)
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11)
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12)
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13)
#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14)
#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15)
/** @} */
/**
* @name CR register constants common to all DMA types
* @{
*/
#define STM32_DMA_CR_EN DMA_SxCR_EN
#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
@ -90,12 +141,15 @@
#define STM32_DMA_CR_MSIZE_BYTE 0
#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_MSIZE_MASK | \
STM32_DMA_CR_MSIZE_MASK)
#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
#define STM32_DMA_CR_PL(n) ((n) << 16)
/** @} */
/**
* @name CR register constants only found in STM32F2xx/STM32F4xx
* @{
*/
#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
@ -118,6 +172,7 @@
/**
* @name FCR register constants only found in STM32F2xx
* @{
*/
#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
@ -176,6 +231,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a peripheral data register to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
@ -357,6 +416,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
#define dmaWaitCompletion(dmastp) \
while (((dmastp)->stream->CNDTR > 0) && \
((dmastp)->stream->CCR & STM32_DMA_CR_EN))
/** @} */
/*===========================================================================*/
/* External declarations. */

13
os/hal/platforms/STM32F4xx/stm32_rcc.h
View File

@ -27,7 +27,6 @@
* @addtogroup STM32F4xx_RCC
* @{
*/
#ifndef _STM32_RCC_
#define _STM32_RCC_
@ -347,7 +346,7 @@
*
* @api
*/
#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHB1ENR_DMA1EN, lp)
#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp)
/**
* @brief Disables the DMA1 peripheral clock.
@ -356,14 +355,14 @@
*
* @api
*/
#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHB1ENR_DMA1EN, lp)
#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp)
/**
* @brief Resets the DMA1 peripheral.
*
* @api
*/
#define rccResetDMA1() rccResetAHB(RCC_AHB1RSTR_DMA1RST)
#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST)
/**
* @brief Enables the DMA2 peripheral clock.
@ -372,7 +371,7 @@
*
* @api
*/
#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHB1ENR_DMA2EN, lp)
#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp)
/**
* @brief Disables the DMA2 peripheral clock.
@ -381,14 +380,14 @@
*
* @api
*/
#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHB1ENR_DMA2EN, lp)
#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp)
/**
* @brief Resets the DMA2 peripheral.
*
* @api
*/
#define rccResetDMA2() rccResetAHB(RCC_AHB1RSTR_DMA2RST)
#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
/** @} */
/**

5
os/hal/platforms/STM32L1xx/adc_lld.h
View File

@ -101,6 +101,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief ADC1 driver enable switch.
* @details If set to @p TRUE the support for ADC1 is included.
@ -134,6 +138,7 @@
#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

5
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -298,6 +298,10 @@
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
@ -456,6 +460,7 @@
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCPRE STM32_RTCPRE_DIV2
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */

51
os/hal/platforms/STM32L1xx/stm32_dma.h
View File

@ -47,21 +47,51 @@
*/
#define STM32_DMA_ISR_MASK 0x0F
/**
* @brief Returns the channel associated to the specified stream.
*
* @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
* @param[in] c a stream/channel association word, one channel per
* nibble, not associated channels must be set to 0xF
* @return Always zero, in this platform there is no dynamic
* association between streams and channels.
*/
#define STM32_DMA_GETCHANNEL(n, c) 0
/**
* @name DMA streams identifiers
* @{
*/
#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0])
#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1])
#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2])
#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3])
#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4])
#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5])
#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6])
/**
* @brief Returns an unique numeric identifier for a DMA stream.
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
*
* @param[in] n the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
* associated to the DMA stream.
*/
#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n))
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
/** @} */
/**
* @name CR register constants common to all DMA types
* @{
*/
#define STM32_DMA_CR_EN DMA_CCR1_EN
#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
@ -88,6 +118,7 @@
/**
* @name CR register constants only found in enhanced DMA
* @{
*/
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
@ -95,6 +126,7 @@
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
#define STM32_DMA_ISR_FEIF 0
#define STM32_DMA_ISR_DMEIF 0
@ -140,6 +172,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a peripheral data register to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
@ -293,6 +329,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
#define dmaWaitCompletion(dmastp) \
while (((dmastp)->channel->CNDTR > 0) && \
((dmastp)->channel->CCR & STM32_DMA_CR_EN))
/** @} */
/*===========================================================================*/
/* External declarations. */

1
os/hal/platforms/STM32L1xx/stm32l1xx.h
View File

@ -430,7 +430,6 @@ typedef struct
__IO uint32_t AFR[2];
} GPIO_TypeDef;
#endif
#endif
/**
* @brief SysTem Configuration

8
readme.txt
View File

@ -74,6 +74,12 @@
*****************************************************************************
*** 2.3.4 ***
- FIX: Fixed Extra initialization in STM32 SPI driver (bug 3436127)
(backported to 2.2.8).
- FIX: Fixed DMA priority setting error in STM32 UART driver (bug 3436125)
(backported to 2.2.8).
- FIX: Fixed DMA priority setting error in STM32 SPI driver (bug 3436124)
(backported to 2.2.8).
- FIX: Fixed broken support for UART5 in STM32 serial driver (bug 3434094)
(backported to 2.2.8).
- FIX: Fixed broken TIM8 support in STM32 PWM driver (bug 3418620).
@ -81,7 +87,7 @@
- NEW: Reorganized the STM32F1xx hal_lld_xxx.h files in order to distribute
the capability macros into the appropriate file (previously those were all
in the common hal_lld.h).
- NEW: Added HAL support for the STM32F4xx sub-family.
- NEW: Added HAL, Serial, SPI support for the STM32F4xx sub-family.
- NEW: Added handling of USART6 to the STM32 serial driver.
- NEW: Added USE_COPT setting to all makefiles, contributed by Mabl.
- NEW: Added EXT driver implementation for AT91SAM7x, contributed by Florian.