From ecd12dd557cc312c51df58fca4e88eb920e792a4 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 16 Aug 2013 08:14:51 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6163
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 21 +++++++--------------
 readme.txt                           |  1 +
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 527711054..ad3a32a0f 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -53,7 +53,6 @@ static void hal_lld_backup_domain_init(void) {
   /* Backup domain access enabled and left open.*/
   PWR->CR |= PWR_CR_DBP;
 
-#if HAL_USE_RTC
   /* Reset BKP domain if different clock source selected.*/
   if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
     /* Backup domain reset.*/
@@ -61,7 +60,13 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR = 0;
   }
 
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+#if STM32_LSE_ENABLED
+  RCC->BDCR |= RCC_BDCR_LSEON;
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                       /* Waits until LSE is stable.   */
+#endif
+
+#if HAL_USE_RTC
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
@@ -71,7 +76,6 @@ static void hal_lld_backup_domain_init(void) {
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;
   }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
 #endif /* HAL_USE_RTC */
 
 #if STM32_BKPRAM_ENABLE
@@ -182,17 +186,6 @@ void stm32_clock_init(void) {
     ;                           /* Waits until LSI is stable.               */
 #endif
 
-#if STM32_LSE_ENABLED
-  /* LSE activation, have to unlock the register.*/
-  if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
-    PWR->CR |= PWR_CR_DBP;
-    RCC->BDCR |= RCC_BDCR_LSEON;
-    PWR->CR &= ~PWR_CR_DBP;
-  }
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                           /* Waits until LSE is stable.               */
-#endif
-
 #if STM32_ACTIVATE_PLL
   /* PLL activation.*/
   RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
diff --git a/readme.txt b/readme.txt
index ebe24bb50..ea4585d99 100644
--- a/readme.txt
+++ b/readme.txt
@@ -114,6 +114,7 @@
   (backported to 2.6.0).
 - FIX: Fixed MS2ST() and US2ST() macros error (bug #415)(backported to 2.6.0,
   2.4.4, 2.2.10, NilRTOS).
+- NEW: Improvements to the STM32F4xx backup domain initialization.
 - NEW: Added initializer for the DIER register to the STM32 GPT, ICU and
   PWM drivers.
 - NEW: Added support for 32bits counters to the STM32 GPT driver.