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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2253 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2010-10-12 20:47:30 +00:00
parent f49c8de5b2
commit ec7455babe
2 changed files with 104 additions and 45 deletions
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103
os/hal/include/adc.h
View File

@ -115,17 +115,106 @@ typedef enum {
} \ } \
} }
#else /* !ADC_USE_WAIT */ /**
* @brief Wakes up the waiting thread.
#define _adc_reset_i(adcp) *
* @param[in] adcp pointer to the @p ADCDriver object
#define _adc_reset_s(adcp) *
* @notapi
#define _adc_isr_code(adcp) { \ */
#define _adc_wakeup_i(adcp) { \
chSysLockFromIsr(); \
(adcp)->ad_grpp = NULL; \
if ((adcp)->ad_thread != NULL) { \
Thread *tp = (adcp)->ad_thread; \
(adcp)->ad_thread = NULL; \
tp->p_u.rdymsg = RDY_OK; \
chSchReadyI(tp); \
} \
chSysUnlockFromIsr(); \
} }
#else /* !ADC_USE_WAIT */
#define _adc_reset_i(adcp)
#define _adc_reset_s(adcp)
#define _adc_wakeup(adcp)
#endif /* !ADC_USE_WAIT */ #endif /* !ADC_USE_WAIT */
/**
* @brief Common ISR code, half buffer full.
* @details This code handles the portable part of the ISR code:
* - Callback invocation.
* .
* @note This macro is meant to be used in the low level drivers
* implementation only.
*
* @param[in] adcp pointer to the @p ADCDriver object
*
* @notapi
*/
#define _adc_isr_half_code(adcp) { \
if ((adcp)->ad_grpp->acg_endcb != NULL) { \
(adcp)->ad_grpp->acg_endcb(adcp, (adcp)->ad_samples, \
(adcp)->ad_depth / 2); \
} \
}
/**
* @brief Common ISR code, full buffer full.
* @details This code handles the portable part of the ISR code:
* - Callback invocation.
* - Waiting thread wakeup, if any.
* - Driver state transitions.
* .
* @note This macro is meant to be used in the low level drivers
* implementation only.
*
* @param[in] adcp pointer to the @p ADCDriver object
*
* @notapi
*/
#define _adc_isr_full_code(adcp) { \
if ((adcp)->ad_grpp->acg_circular) { \
/* Callback handling.*/ \
if ((adcp)->ad_grpp->acg_endcb != NULL) { \
if ((adcp)->ad_depth > 1) { \
/* Invokes the callback passing the 2nd half of the buffer.*/ \
size_t half = (adcp)->ad_depth / 2; \
(adcp)->ad_grpp->acg_endcb(adcp, (adcp)->ad_samples + half, half); \
} \
else { \
/* Invokes the callback passing the whole buffer.*/ \
(adcp)->ad_grpp->acg_endcb(adcp, (adcp)->ad_samples, \
(adcp)->ad_depth); \
} \
} \
} \
else { \
(adcp)->ad_grpp = NULL; \
/* End conversion.*/ \
adc_lld_stop_conversion(adcp); \
if ((adcp)->ad_grpp->acg_endcb == NULL) { \
(adcp)->ad_state = ADC_READY; \
_adc_wakeup_i(adcp); \
} \
else { \
(adcp)->ad_state = ADC_COMPLETE; \
if ((adcp)->ad_depth > 1) { \
/* Invokes the callback passing the 2nd half of the buffer.*/ \
size_t half = (adcp)->ad_depth / 2; \
(adcp)->ad_grpp->acg_endcb(adcp, (adcp)->ad_samples + half, half); \
} \
else { \
/* Invokes the callback passing the whole buffer.*/ \
(adcp)->ad_grpp->acg_endcb(adcp, (adcp)->ad_samples, \
(adcp)->ad_depth); \
} \
if ((adcp)->ad_state == ADC_COMPLETE) \
(adcp)->ad_state = ADC_READY; \
} \
} \
}
/*===========================================================================*/ /*===========================================================================*/
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/

46
os/hal/platforms/STM32/adc_lld.c
View File

@ -64,48 +64,18 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
isr = STM32_DMA1->ISR; isr = STM32_DMA1->ISR;
dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_1); dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_1);
if ((isr & DMA_ISR_HTIF1) != 0) {
/* Half transfer processing.*/
if (ADCD1.ad_grpp->acg_endcb != NULL) {
/* Invokes the callback passing the 1st half of the buffer.*/
ADCD1.ad_grpp->acg_endcb(&ADCD1, ADCD1.ad_samples, ADCD1.ad_depth / 2);
}
}
if ((isr & DMA_ISR_TCIF1) != 0) {
/* Transfer complete processing.*/
if (!ADCD1.ad_grpp->acg_circular) {
/* End conversion.*/
adc_lld_stop_conversion(&ADCD1);
ADCD1.ad_grpp = NULL;
ADCD1.ad_state = ADC_COMPLETE;
#if ADC_USE_WAIT
chSysLockFromIsr();
if (ADCD1.ad_thread != NULL) {
Thread *tp = ADCD1.ad_thread;
ADCD1.ad_thread = NULL;
tp->p_u.rdymsg = RDY_OK;
chSchReadyI(tp);
}
chSysUnlockFromIsr();
#endif
}
/* Callback handling.*/
if (ADCD1.ad_grpp->acg_endcb != NULL) {
if (ADCD1.ad_depth > 1) {
/* Invokes the callback passing the 2nd half of the buffer.*/
size_t half = ADCD1.ad_depth / 2;
ADCD1.ad_grpp->acg_endcb(&ADCD1, ADCD1.ad_samples + half, half);
}
else {
/* Invokes the callback passing the whole buffer.*/
ADCD1.ad_grpp->acg_endcb(&ADCD1, ADCD1.ad_samples, ADCD1.ad_depth);
}
}
}
if ((isr & DMA_ISR_TEIF1) != 0) { if ((isr & DMA_ISR_TEIF1) != 0) {
/* DMA error processing.*/ /* DMA error processing.*/
STM32_ADC1_DMA_ERROR_HOOK(); STM32_ADC1_DMA_ERROR_HOOK();
} }
if ((isr & DMA_ISR_HTIF1) != 0) {
/* Half transfer processing.*/
_adc_isr_half_code(&ADCD1);
}
if ((isr & DMA_ISR_TCIF1) != 0) {
/* Transfer complete processing.*/
_adc_isr_full_code(&ADCD1);
}
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
} }