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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5177 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-02-13 12:54:44 +00:00
parent 24469eee45
commit ec0a1f48ad
2 changed files with 217 additions and 32 deletions
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164
docs/reports/SPC56EL60-120.txt Normal file
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@ -0,0 +1,164 @@
***************************************************************************
Options: -O2 -fomit-frame-pointer -falign-functions=16
Settings: SYSCLK=120
***************************************************************************
*** ChibiOS/RT test suite
***
*** Kernel: 2.5.2unstable
*** Compiled: Feb 13 2013 - 12:33:56
*** Compiler: GCC 4.6.3 build on 2013-01-07
*** Architecture: Power Architecture
*** Core Variant: e200z4
*** Port Info: VLE mode
*** Platform: SPC56ELxx Chassis and Safety
*** Test Board: Generic SPC56ELxx
----------------------------------------------------------------------------
--- Test Case 1.1 (Threads, enqueuing test #1)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.2 (Threads, enqueuing test #2)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.3 (Threads, priority change)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 1.4 (Threads, delays)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.1 (Semaphores, enqueuing)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.2 (Semaphores, timeout)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.3 (Semaphores, atomic signal-wait)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 2.4 (Binary Semaphores, functionality)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.1 (Mutexes, priority enqueuing test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.2 (Mutexes, priority inheritance, simple case)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.3 (Mutexes, priority inheritance, complex case)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.4 (Mutexes, priority return)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.5 (Mutexes, status)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.6 (CondVar, signal test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.7 (CondVar, broadcast test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 3.8 (CondVar, boost test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 4.1 (Messages, loop)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 5.1 (Mailboxes, queuing and timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.1 (Events, registration and dispatch)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.2 (Events, wait and broadcast)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 6.3 (Events, timeouts)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 7.1 (Heap, allocation and fragmentation test)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 8.1 (Memory Pools, queue/dequeue)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.1 (Dynamic APIs, threads creation from heap)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 9.3 (Dynamic APIs, registry and references)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.1 (Queues, input queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 10.2 (Queues, output queues)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
--- Score : 378081 msgs/S, 756162 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
--- Score : 312112 msgs/S, 624224 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
--- Score : 312115 msgs/S, 624230 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
--- Score : 1099584 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
--- Score : 244343 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
--- Score : 369918 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
--- Score : 94519 reschedules/S, 567114 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
--- Score : 633460 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
--- Score : 1104628 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
--- Score : 1295758 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
--- Score : 1762552 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
--- Score : 1227172 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
--- System: 1052 bytes
--- Thread: 72 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- EventS: 4 bytes
--- EventL: 16 bytes
--- Mutex : 16 bytes
--- CondV.: 8 bytes
--- Queue : 36 bytes
--- MailB.: 40 bytes
--- Result: SUCCESS
----------------------------------------------------------------------------
Final result: SUCCESS

85
os/ports/GCC/PPC/SPC56ELxx/core.s
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@ -107,6 +107,13 @@
#define MAS3_SR 0x00000001 #define MAS3_SR 0x00000001
/** @} */ /** @} */
/**
* @name LICSR1 registers definitions
* @{
*/
#define LICSR1_ICE 0x00000001
/** @} */
/** /**
* @name MSR default settings * @name MSR default settings
*/ */
@ -144,6 +151,13 @@
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
/** @} */ /** @} */
/**
* @name LICSR1 default settings
* @{
*/
#define LICSR1_DEFAULT (LICSR1_ICE)
/** @} */
#if !defined(__DOXYGEN__) #if !defined(__DOXYGEN__)
.section .handlers, "ax" .section .handlers, "ax"
@ -300,7 +314,7 @@ _coreinit:
mtspr 413, %r3 mtspr 413, %r3
mtspr 414, %r3 mtspr 414, %r3
mtspr 415, %r3 mtspr 415, %r3
mtspr 528, %r3 /* IVOR32-34 */ mtspr 528, %r3 /* IVOR32-34 */
mtspr 529, %r3 mtspr 529, %r3
mtspr 530, %r3 mtspr 530, %r3
@ -308,110 +322,117 @@ _coreinit:
* TLB0 allocated to flash. * TLB0 allocated to flash.
*/ */
lis %r3, TLB0_MAS0@h lis %r3, TLB0_MAS0@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
lis %r3, TLB0_MAS1@h lis %r3, TLB0_MAS1@h
ori %r3, %r3, TLB0_MAS1@l ori %r3, %r3, TLB0_MAS1@l
mtspr 625, %r3 /* MAS1 */ mtspr 625, %r3 /* MAS1 */
lis %r3, TLB0_MAS2@h lis %r3, TLB0_MAS2@h
ori %r3, %r3, TLB0_MAS2@l ori %r3, %r3, TLB0_MAS2@l
mtspr 626, %r3 /* MAS2 */ mtspr 626, %r3 /* MAS2 */
lis %r3, TLB0_MAS3@h lis %r3, TLB0_MAS3@h
ori %r3, %r3, TLB0_MAS3@l ori %r3, %r3, TLB0_MAS3@l
mtspr 627, %r3 /* MAS3 */ mtspr 627, %r3 /* MAS3 */
tlbwe tlbwe
/* /*
* TLB1 allocated to internal RAM. * TLB1 allocated to internal RAM.
*/ */
lis %r3, TLB1_MAS0@h lis %r3, TLB1_MAS0@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
lis %r3, TLB1_MAS1@h lis %r3, TLB1_MAS1@h
ori %r3, %r3, TLB1_MAS1@l ori %r3, %r3, TLB1_MAS1@l
mtspr 625, %r3 /* MAS1 */ mtspr 625, %r3 /* MAS1 */
lis %r3, TLB1_MAS2@h lis %r3, TLB1_MAS2@h
ori %r3, %r3, TLB1_MAS2@l ori %r3, %r3, TLB1_MAS2@l
mtspr 626, %r3 /* MAS2 */ mtspr 626, %r3 /* MAS2 */
lis %r3, TLB1_MAS3@h lis %r3, TLB1_MAS3@h
ori %r3, %r3, TLB1_MAS3@l ori %r3, %r3, TLB1_MAS3@l
mtspr 627, %r3 /* MAS3 */ mtspr 627, %r3 /* MAS3 */
tlbwe tlbwe
/* /*
* TLB2 allocated to internal Peripherals Bridge A. * TLB2 allocated to internal Peripherals Bridge A.
*/ */
lis %r3, TLB2_MAS0@h lis %r3, TLB2_MAS0@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
lis %r3, TLB2_MAS1@h lis %r3, TLB2_MAS1@h
ori %r3, %r3, TLB2_MAS1@l ori %r3, %r3, TLB2_MAS1@l
mtspr 625, %r3 /* MAS1 */ mtspr 625, %r3 /* MAS1 */
lis %r3, TLB2_MAS2@h lis %r3, TLB2_MAS2@h
ori %r3, %r3, TLB2_MAS2@l ori %r3, %r3, TLB2_MAS2@l
mtspr 626, %r3 /* MAS2 */ mtspr 626, %r3 /* MAS2 */
lis %r3, TLB2_MAS3@h lis %r3, TLB2_MAS3@h
ori %r3, %r3, TLB2_MAS3@l ori %r3, %r3, TLB2_MAS3@l
mtspr 627, %r3 /* MAS3 */ mtspr 627, %r3 /* MAS3 */
tlbwe tlbwe
/* /*
* TLB3 allocated to internal Peripherals Bridge B. * TLB3 allocated to internal Peripherals Bridge B.
*/ */
lis %r3, TLB3_MAS0@h lis %r3, TLB3_MAS0@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
lis %r3, TLB3_MAS1@h lis %r3, TLB3_MAS1@h
ori %r3, %r3, TLB3_MAS1@l ori %r3, %r3, TLB3_MAS1@l
mtspr 625, %r3 /* MAS1 */ mtspr 625, %r3 /* MAS1 */
lis %r3, TLB3_MAS2@h lis %r3, TLB3_MAS2@h
ori %r3, %r3, TLB3_MAS2@l ori %r3, %r3, TLB3_MAS2@l
mtspr 626, %r3 /* MAS2 */ mtspr 626, %r3 /* MAS2 */
lis %r3, TLB3_MAS3@h lis %r3, TLB3_MAS3@h
ori %r3, %r3, TLB3_MAS3@l ori %r3, %r3, TLB3_MAS3@l
mtspr 627, %r3 /* MAS3 */ mtspr 627, %r3 /* MAS3 */
tlbwe tlbwe
/* /*
* Invalidating the remaining TLBs (because debuggers). * Invalidating the remaining TLBs (because debuggers).
*/ */
lis %r3, 0 lis %r3, 0
mtspr 625, %r3 /* MAS1 */ mtspr 625, %r3 /* MAS1 */
mtspr 626, %r3 /* MAS2 */ mtspr 626, %r3 /* MAS2 */
mtspr 627, %r3 /* MAS3 */ mtspr 627, %r3 /* MAS3 */
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
mtspr 624, %r3 /* MAS0 */ mtspr 624, %r3 /* MAS0 */
tlbwe tlbwe
/*
* Cache enabled.
*/
mfspr %r3, 1011 /* LICSR1 */
ori %r3, %r3, LICSR1_DEFAULT
mtspr 1011, %r3 /* LICSR1 */
blr blr
#endif /* !defined(__DOXYGEN__) */ #endif /* !defined(__DOXYGEN__) */