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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2151 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2010-08-31 18:17:11 +00:00
parent 7b11d85a8a
commit ebe5a80200
1 changed files with 8 additions and 8 deletions
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16
os/ports/GCC/ARMCMx/old/chcore_v7m.h
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@ -164,11 +164,11 @@ struct intctx {
#if CH_OPTIMIZE_SPEED #if CH_OPTIMIZE_SPEED
#define port_lock() { \ #define port_lock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
} }
#else #else
#define port_lock() { \ #define port_lock() { \
asm volatile ("bl _port_lock" : : : "r3", "lr"); \ asm volatile ("bl _port_lock" : : : "r3", "lr", "memory"); \
} }
#endif #endif
@ -181,11 +181,11 @@ struct intctx {
#if CH_OPTIMIZE_SPEED #if CH_OPTIMIZE_SPEED
#define port_unlock() { \ #define port_unlock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ asm volatile ("msr BASEPRI, %0" : : "r" (tmp) : "memory"); \
} }
#else #else
#define port_unlock() { \ #define port_unlock() { \
asm volatile ("bl _port_unlock" : : : "r3", "lr"); \ asm volatile ("bl _port_unlock" : : : "r3", "lr", "memory"); \
} }
#endif #endif
@ -213,7 +213,7 @@ struct intctx {
* @note In this port it disables all the interrupt sources by raising * @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0. * the priority mask to level 0.
*/ */
#define port_disable() asm volatile ("cpsid i") #define port_disable() asm volatile ("cpsid i" : : : "memory")
/** /**
* @brief Disables the interrupt sources below kernel-level priority. * @brief Disables the interrupt sources below kernel-level priority.
@ -223,7 +223,7 @@ struct intctx {
#define port_suspend() { \ #define port_suspend() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \ asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \ "cpsie i" : : "r" (tmp) : "memory"); \
} }
/** /**
@ -233,7 +233,7 @@ struct intctx {
#define port_enable() { \ #define port_enable() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0 \n\t" \ asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \ "cpsie i" : : "r" (tmp) : "memory"); \
} }
/** /**
@ -246,7 +246,7 @@ struct intctx {
*/ */
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) #if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() { \ #define port_wait_for_interrupt() { \
asm volatile ("wfi"); \ asm volatile ("wfi" : : : "memory"); \
} }
#else #else
#define port_wait_for_interrupt() #define port_wait_for_interrupt()