Better clock settings.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8486 35acf78f-673a-0410-8e92-d51de3d6d3f4master
Giovanni Di Sirio
parent
2698f6f13e
commit
ea4c40fc0d
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@ -40,7 +40,7 @@
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#define STM32_VOS STM32_VOS_RANGE1
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI16_ENABLED FALSE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSE_ENABLED TRUE
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@ -52,12 +52,12 @@
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#define STM32_MSIRANGE STM32_MSIRANGE_4M
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#define STM32_MSISRANGE STM32_MSISRANGE_4M
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#define STM32_SW STM32_SW_PLL
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#define STM32_PLLSRC STM32_PLLSRC_HSI16
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#define STM32_PLLM_VALUE 4
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#define STM32_PLLN_VALUE 40
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#define STM32_PLLSRC STM32_PLLSRC_MSI
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#define STM32_PLLM_VALUE 1
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#define STM32_PLLN_VALUE 80
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#define STM32_PLLP_VALUE 7
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLR_VALUE 2
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#define STM32_PLLQ_VALUE 6
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#define STM32_PLLR_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE1 STM32_PPRE1_DIV1
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#define STM32_PPRE2 STM32_PPRE2_DIV1
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@ -65,11 +65,11 @@
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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#define STM32_PLLSAI1N_VALUE 40
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#define STM32_PLLSAI1N_VALUE 80
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#define STM32_PLLSAI1P_VALUE 7
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#define STM32_PLLSAI1Q_VALUE 4
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#define STM32_PLLSAI1Q_VALUE 6
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#define STM32_PLLSAI1R_VALUE 4
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#define STM32_PLLSAI2N_VALUE 40
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#define STM32_PLLSAI2N_VALUE 80
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#define STM32_PLLSAI2P_VALUE 7
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#define STM32_PLLSAI2R_VALUE 4
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#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
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@ -357,7 +357,7 @@
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* @brief Enables or disables the HSI16 clock source.
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*/
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#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSI16_ENABLED FALSE
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#endif
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/**
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@ -435,7 +435,7 @@
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* @note If the selected clock source is not the PLL then the PLL is not
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* initialized and started.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 16MHz HSI clock.
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_SW) || defined(__DOXYGEN__)
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#define STM32_SW STM32_SW_PLL
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@ -446,37 +446,37 @@
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 16MHz HSI clock.
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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#define STM32_PLLSRC STM32_PLLSRC_HSI16
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#define STM32_PLLSRC STM32_PLLSRC_MSI
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#endif
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/**
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* @brief PLLM divider value.
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* @note The allowed values are 1..8.
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* @note The default value is calculated for a 80MHz system clock from
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* an external 8MHz HSE clock.
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLM_VALUE 4
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#define STM32_PLLM_VALUE 1
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#endif
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/**
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* @brief PLLN multiplier value.
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* @note The allowed values are 8..86.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 16MHz HSI clock.
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLN_VALUE 40
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#define STM32_PLLN_VALUE 80
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#endif
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/**
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* @brief PLLP divider value.
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* @note The allowed values are 7, 17.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 16MHz HSI clock.
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLP_VALUE 7
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@ -485,27 +485,27 @@
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/**
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* @brief PLLQ divider value.
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* @note The allowed values are 2, 4, 6, 8.
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* @note The default value is calculated for a 216MHz system clock from
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* an external 25MHz HSE clock.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLQ_VALUE 2
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#define STM32_PLLQ_VALUE 6
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#endif
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/**
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* @brief PLLR divider value.
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* @note The allowed values are 2, 4, 6, 8.
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* @note The default value is calculated for a 216MHz system clock from
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* an external 25MHz HSE clock.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLR_VALUE 2
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#define STM32_PLLR_VALUE 4
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#endif
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/**
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* @brief AHB prescaler value.
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* @note The default value is calculated for a 32MHz system clock from
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* the internal 16MHz HSI clock.
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* @note The default value is calculated for a 80MHz system clock from
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* the internal 4MHz MSI clock.
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*/
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#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
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#define STM32_HPRE STM32_HPRE_DIV1
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@ -558,7 +558,7 @@
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* @note The allowed values are 8..86.
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*/
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#if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLSAI1N_VALUE 40
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#define STM32_PLLSAI1N_VALUE 80
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#endif
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/**
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@ -574,7 +574,7 @@
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* @note The allowed values are 2, 4, 6, 8.
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*/
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#if !defined(STM32_PLLSAI1Q_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLSAI1Q_VALUE 4
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#define STM32_PLLSAI1Q_VALUE 6
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#endif
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/**
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@ -590,7 +590,7 @@
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* @note The allowed values are 8..86.
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*/
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#if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLSAI2N_VALUE 40
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#define STM32_PLLSAI2N_VALUE 80
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#endif
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/**
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@ -956,7 +956,7 @@
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#endif
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/*
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* HSI related checks.
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* HSI16 related checks.
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*/
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#if STM32_HSI16_ENABLED
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#else /* !STM32_HSI16_ENABLED */
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@ -969,7 +969,7 @@
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#error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC"
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#endif
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#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
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#if (STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
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((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
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(STM32_PLLSRC == STM32_PLLSRC_HSI16))
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#error "HSI16 not enabled, required by STM32_MCOSEL"
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@ -984,7 +984,7 @@
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#if ((STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI1) || \
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(STM32_SAI2SEL == STM32_SAI1SEL_PLLSAI2)) && \
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(STM32_PLLSRC == STM32_PLLSRC_HSI16)
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#error "HSI not enabled, required by STM32_SAI2SEL"
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#error "HSI16 not enabled, required by STM32_SAI2SEL"
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#endif
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#endif /* !STM32_HSI16_ENABLED */
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@ -1416,7 +1416,7 @@
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*/
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#if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
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(STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI1) || \
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(STM32_CLK48SEL == STM32_CLK48SEL_PLL) || \
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(STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1) || \
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(STM32_ADCSEL == STM32_ADCSEL_PLLSAI1) || \
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defined(__DOXYGEN__)
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/**
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