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[KINETIS] Config option for FEI mode + PEE config moved 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7179 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
utzig 2014-08-19 12:02:36 +00:00
parent eb37222a0e
commit dd8d02ae8e
2 changed files with 14 additions and 7 deletions
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16
demos/KINETIS/RT-FREEDOM-K20D50M/mcuconf.h
View File

@ -22,10 +22,22 @@
/* Select the MCU clocking mode below by enabling the appropriate block. */
/* FEI mode */
/* Disable all clock intialization */
#define KINETIS_NO_INIT FALSE
/* PEE mode - external 8 MHz crystal with PLL for 48 MHz core/system clock. */
#if 1
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
#define KINETIS_XTAL_FREQUENCY 8000000UL
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#endif
/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
#if 0
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
#define KINETIS_SYSCLK_FREQUENCY 21000000UL
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#endif /* 0 */
/* FEE mode - 24 MHz with external 32.768 kHz crystal */

5
os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h
View File

@ -27,11 +27,6 @@
#define BOARD_FREESCALE_FREEDOM_K20D50M
#define BOARD_NAME "Freescale Freedom K20D50M"
/* External 8 MHz crystal with PLL for 48 MHz core/system clock. */
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
#define KINETIS_XTAL_FREQUENCY 8000000UL
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {