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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7064 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2014-07-24 07:29:41 +00:00
parent 37de072555
commit dd1dc10973
18 changed files with 788 additions and 154 deletions
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64
os/common/ports/e200/compilers/GCC/vectors.h
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@ -35,18 +35,6 @@
/* Module constants. */ /* Module constants. */
/*===========================================================================*/ /*===========================================================================*/
#if PPC_INTC_TYPE == 0
#define INTC_IACKR_ADDR (PPC_INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (PPC_INTC_BASE + 0x18)
#elif PPC_INTC_TYPE == 1
#define INTC_IACKR_ADDR (PPC_INTC_BASE + 0x20)
#define INTC_EOIR_ADDR (PPC_INTC_BASE + 0x30)
#else
#error "unknown INTC type"
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Module pre-compile time settings. */ /* Module pre-compile time settings. */
/*===========================================================================*/ /*===========================================================================*/
@ -63,40 +51,6 @@
/* Module macros. */ /* Module macros. */
/*===========================================================================*/ /*===========================================================================*/
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
/**
* @name INTC-related macros
* @{
*/
#if PPC_INTC_TYPE == 0
#define INTC_BCR (*((volatile uint32_t *)(PPC_INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(PPC_INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(PPC_INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(PPC_INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(PPC_INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
#elif PPC_INTC_TYPE == 1
#define INTC_BCR (*((volatile uint32_t *)(PPC_INTC_BASE + 0)))
#define INTC_MPROT (*((volatile uint32_t *)(PPC_INTC_BASE + 4)))
#define INTC_CPR(n) (*((volatile uint32_t *)(PPC_INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(PPC_INTC_BASE + 0x20 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(PPC_INTC_BASE + 0x30 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint16_t *)(PPC_INTC_BASE + 0x60 + ((n) * sizeof (uint16_t)))))
#else
#error "unknown INTC type"
#endif
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
#endif /* !defined(_FROM_ASM_) */
/*===========================================================================*/ /*===========================================================================*/
/* External declarations. */ /* External declarations. */
/*===========================================================================*/ /*===========================================================================*/
@ -123,24 +77,6 @@ extern "C" {
/* Module inline functions. */ /* Module inline functions. */
/*===========================================================================*/ /*===========================================================================*/
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
static inline void intc_init(void) {
unsigned i;
/* INTC initialization, software vector mode, 4 bytes vectors, starting
at priority 0.*/
INTC_BCR = 0;
for (i = 0; i < PPC_CORE_NUMBER; i++) {
INTC_CPR(i) = 0;
INTC_IACKR(i) = (uint32_t)_vectors;
}
}
#endif /* !defined(_FROM_ASM_) */
#endif /* _VECTORS_H_ */ #endif /* _VECTORS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC560BCxx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC560BCxx/intc.h
* @brief SPC560BCxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC560BCxx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC560BCxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 217 #define PPC_NUM_VECTORS 217
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC560Bxx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC560Bxx/intc.h
* @brief SPC560Bxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC560Bxx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC560Bxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 234 #define PPC_NUM_VECTORS 234
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC560Dxx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC560Dxx/intc.h
* @brief SPC560Dxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC560Dxx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC560Dxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 155 #define PPC_NUM_VECTORS 155
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC560Pxx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC560Pxx/intc.h
* @brief SPC560Pxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC560Pxx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC560Pxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 261 #define PPC_NUM_VECTORS 261
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC563Mxx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC563Mxx/intc.h
* @brief SPC563Mxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC563Mxx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC563Mxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 360 #define PPC_NUM_VECTORS 360
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC564Axx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC564Axx/intc.h
* @brief SPC564Axx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC564Axx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC564Axx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 486 #define PPC_NUM_VECTORS 486
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

94
os/common/ports/e200/devices/SPC56ECxx/intc.h Normal file
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@ -0,0 +1,94 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC56ECxx/intc.h
* @brief SPC56ECxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
#define INTC_PSR_CORE1 0xC0
#define INTC_PSR_CORES01 0x40
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC56ECxx/ppcparams.h
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@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC56ECxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 279 #define PPC_NUM_VECTORS 279
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

92
os/common/ports/e200/devices/SPC56ELxx/intc.h Normal file
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@ -0,0 +1,92 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file SPC56ELxx/intc.h
* @brief SPC56ELxx INTC module header.
*
* @addtogroup INTC
* @{
*/
#ifndef _INTC_H_
#define _INTC_H_
/*===========================================================================*/
/* Module constants. */
/*===========================================================================*/
/**
* @name INTC addresses
* @{
*/
#define INTC_BASE 0xFFF48000
#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
/** @} */
/*===========================================================================*/
/* Module pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Module data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Module macros. */
/*===========================================================================*/
/**
* @name INTC-related macros
* @{
*/
#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
/** @} */
/**
* @brief Core selection macros for PSR register.
*/
#define INTC_PSR_CORE0 0x00
/**
* @brief PSR register content helper
*/
#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/*===========================================================================*/
/* Module inline functions. */
/*===========================================================================*/
#endif /* _INTC_H_ */
/** @} */

16
os/common/ports/e200/devices/SPC56ELxx/ppcparams.h
View File

@ -32,6 +32,11 @@
#ifndef _PPCPARAMS_H_ #ifndef _PPCPARAMS_H_
#define _PPCPARAMS_H_ #define _PPCPARAMS_H_
/**
* @brief Family identification macro.
*/
#define PPC_SPC56ELxx
/** /**
* @brief PPC core model. * @brief PPC core model.
*/ */
@ -77,17 +82,6 @@
*/ */
#define PPC_NUM_VECTORS 256 #define PPC_NUM_VECTORS 256
/**
* @brief Memory address of the INTC controller.
*/
#define PPC_INTC_BASE 0xFFF48000
/**
* @brief Type of the INTC controller.
* @note 0=SPC56x, 1=SPC57x.
*/
#define PPC_INTC_TYPE 0
#endif /* _PPCPARAMS_H_ */ #endif /* _PPCPARAMS_H_ */
/** @} */ /** @} */

12
os/nil/ports/e200/nilcore.h
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@ -29,6 +29,8 @@
#ifndef _NILCORE_H_ #ifndef _NILCORE_H_
#define _NILCORE_H_ #define _NILCORE_H_
#include "intc.h"
/*===========================================================================*/ /*===========================================================================*/
/* Module constants. */ /* Module constants. */
/*===========================================================================*/ /*===========================================================================*/
@ -368,6 +370,7 @@ extern "C" {
*/ */
static inline void port_init(void) { static inline void port_init(void) {
uint32_t n; uint32_t n;
unsigned i;
/* Initializing the SPRG0 register to zero, it is required for interrupts /* Initializing the SPRG0 register to zero, it is required for interrupts
handling.*/ handling.*/
@ -383,8 +386,13 @@ static inline void port_init(void) {
"mtIVOR10 %%r3" : : : "r3", "memory"); "mtIVOR10 %%r3" : : : "r3", "memory");
#endif #endif
/* Interrupt controller initialization.*/ /* INTC initialization, software vector mode, 4 bytes vectors, starting
intc_init(); at priority 0.*/
INTC_BCR = 0;
for (i = 0; i < PPC_CORE_NUMBER; i++) {
INTC_CPR(i) = 0;
INTC_IACKR(i) = (uint32_t)_vectors;
}
} }
/** /**